PLS extends MCU profiling beyond trace hardware

PLS extends MCU profiling beyond trace hardware

PLS has widened MCU runtime profiling beyond dedicated trace hardware. UDE 2026 adds CPU-load sampling through the debug interface, opening analysis to microcontrollers where trace support is limited or absent.


IN Brief:

  • UDE 2026 adds CPU-load sampling through the debug interface as an alternative to trace-based profiling.
  • The feature broadens runtime analysis to MCUs without dedicated trace support, with some loss in statistical accuracy.
  • The release also expands AUTOSAR analysis, Python script debugging, virtualisation trace support, and MCU architecture coverage.

PLS has expanded the scope of its Universal Debug Engine 2026 by adding CPU utilisation sampling through the debug interface, giving developers a way to profile runtime behaviour on microcontrollers that do not offer dedicated trace support.

That shift is more consequential than it first appears. Trace-based analysis remains the cleaner route where hardware support exists, but it is not universal, especially across cost-sensitive or legacy MCU families. PLS said the new sampling method trades some statistical accuracy for far wider applicability, allowing developers to calculate CPU load for RTOS and AUTOSAR-based applications even when on-chip trace resources are unavailable.

The wider UDE 2026 release adds more than that. PLS has introduced extra AUTOSAR Runtime Interface hooks so service calls and spinlocks can be visualised alongside tasks and interrupts, and it has added a dedicated debugger for Python scripts running inside the integrated Python console. On the device side, the company has expanded support for controllers including Infineon AURIX TC4Dx, NXP’s S32K5 family, STMicroelectronics’ STM32H5, TI’s MSPM0 and MSPM33, Tongxin Micro’s THA6 Gen2 automotive MCUs, and Andes-based RISC-V cores.

PLS has also been broadening UDE 2026 around newer compute models, including debug and runtime analysis support for Bosch’s Data Flow Architecture accelerators used in embedded AI. Taken together, the release reflects a debugger platform being stretched to cover a more fragmented MCU landscape, where trace availability, software complexity, virtualisation, and accelerator blocks are no longer edge cases. More detail is available on the UDE 2026 release page.


Stories for you


  • Molex moves for Teramount in CPO push

    Molex moves for Teramount in CPO push

    Molex has agreed to acquire Teramount, adding detachable passive-alignment fiber-to-chip technology to its co-packaged optics stack as AI-driven data-centre optics moves closer to scale.


  • Synopsys delivers complete UFS 5.0 IP stack for next-gen storage

    Synopsys delivers complete UFS 5.0 IP stack for next-gen storage

    Synopsys has rolled out a complete UFS 5.0, UniPro 3.0, and M-PHY v6.0 IP solution for next-generation storage, combining protocol, link, and physical layers in a single stack as edge-AI and automotive SoCs push storage bandwidth into a system-level constraint.