IN Brief:
- PGY-UFS5-EX-PA supports MIPI M-PHY v6.0, UniPro v3.0, and JEDEC UFS 5.0.
- The platform operates at up to 46.64Gbps per lane and addresses PAM4 signal acquisition and protocol validation.
- Exerciser, continuous capture, real-time decoding, packet triggering, and error-analysis functions are combined in one tool.
Prodigy Technovations has launched the PGY-UFS5-EX-PA protocol exerciser and analyser for Universal Flash Storage 5.0, supporting interface operation at up to 46.64Gbps per lane. The platform covers MIPI M-PHY v6.0, MIPI UniPro v3.0, and JEDEC UFS 5.0, combining traffic generation, acquisition, protocol decoding, triggering, and error analysis for engineers developing next-generation embedded storage devices and controllers.
UFS 5.0 moves the interface into the HSG6B signalling regime, using PAM4 to increase the amount of information transmitted within a given symbol rate. Four amplitude levels encode two bits per symbol rather than the single bit carried by conventional NRZ signalling, increasing effective throughput but reducing the electrical margin between valid signal levels.
That change makes acquisition more demanding. Jitter, noise, channel loss, equalisation, probe loading, and receiver behaviour all become harder to separate when the signal contains four decision levels, so a protocol analyser working at UFS 5.0 speeds has to capture the physical transaction reliably before its higher-level decode becomes useful.
Prodigy says PGY-UFS5-EX-PA supports continuous streaming of protocol traffic alongside real-time decoding and error analysis. The continuous-capture capability addresses a practical problem created by the interface speed: at 46.64Gbps per lane, a long trace can consume local acquisition memory rapidly, while an intermittent fault may occur well after the link has completed normal initialisation.
Streaming data to a larger host-side capture path extends the observable period, allowing engineers to investigate failures that depend on long command sequences or changes in device state. The trade-off shifts towards host-storage throughput, data management, and analysis software because collecting a larger trace is only valuable if the engineer can isolate the transaction that explains the fault.
Protocol-aware triggering helps narrow that search. The platform can trigger against content at the M-PHY, UniPro, and UFS layers rather than relying only on an electrical event. Engineers can therefore stop or mark acquisition around particular packets, commands, states, or error conditions and inspect what happened immediately before and after the event.
The exerciser function provides the opposite side of the test loop by generating controlled traffic towards the device under test. That can be used to recreate known sequences, explore boundary conditions, and determine whether a failure originates in a UFS controller, PHY, firmware implementation, or interaction between layers. Combining exerciser and analyser functions also reduces the need to synchronise separate pieces of equipment around one test scenario.
The higher interface rate arrives as embedded storage is being asked to support increasingly demanding application processors and AI workloads. On-device inference can involve large model files and repeated movement of data between flash, DRAM, and processing resources, while automotive systems combine logging, maps, sensor data, infotainment, application software, and increasingly capable compute platforms.
Faster storage does not remove bottlenecks elsewhere in those systems, but an interface that cannot feed the processor consistently can waste performance available in the compute and memory subsystem. Equally, an interface that reaches its target throughput but fails under particular state transitions or error conditions is of little value in a production device, making validation of the full protocol stack as important as headline bandwidth.
The test burden consequently spans several engineering disciplines. PHY design, controller RTL, package behaviour, PCB layout, firmware, protocol implementation, clocking, power management, and host software can all contribute to a transaction failure. A protocol tool cannot replace oscilloscope or compliance work at the electrical layer, but it gives engineers a common view of how those electrical conditions appear to the protocol above them.
Prodigy already supplies analysis and test equipment for interfaces including PCI Express, eMMC, SD, I3C, RFFE, and SPMI and participates as a contributor member of the MIPI Alliance, including the M-PHY and UniPro working groups. PGY-UFS5-EX-PA extends that portfolio into the latest UFS generation rather than representing a standalone storage product.
The platform is available to order now, with pricing supplied on request. Its practical value will depend on probe options, automation, capture performance, interoperability with early UFS 5.0 silicon, and the ability of its software to turn very large traces into useful fault evidence. At 46.64Gbps per lane, validation is increasingly about finding the right transaction quickly rather than simply proving that data appeared on the bus.
