Sandisk expands NAND roadmap for AI storage

Sandisk has outlined a NAND technology roadmap combining new wafer-bonding strategies, higher-density QLC flash, and emerging high-bandwidth storage as AI inference changes the amount and location of data stored around compute accelerators.

The company is developing what it describes as a two-dimensional scaling strategy based on CMOS directly Bonded to Array technology. Instead of tying every NAND generation to one fixed combination of memory array and peripheral CMOS, Sandisk can combine elements from different technology generations to create derivatives for particular performance, capacity, and manufacturing requirements.

BiCS9 QLC is the first example. Sandisk says the device combines its established BiCS8 memory array with a CMOS wafer based on BiCS10 technology, allowing the company to introduce newer peripheral circuitry without waiting for both halves of the NAND device to move together to an entirely new process generation.

The approach reflects the changing difficulty of NAND scaling. Adding more memory layers increases potential storage density, but the completed device still depends on page buffers, control logic, interfaces, error correction, and power-management circuits capable of accessing and managing that array at useful speed.

Fabricating the memory array and CMOS separately before bonding gives the manufacturer more freedom to optimise each. The trade is that wafer bonding becomes another critical production stage, with alignment, bond quality, interconnect integrity, thermal processing, and yield all capable of affecting the completed device.

Sandisk is also developing BiCS10 QLC, which it says will increase bit density by 60% compared with BiCS8. Density remains fundamental to NAND economics because extracting more usable bits from a wafer can lower manufacturing cost per stored bit, provided yield, endurance, and performance remain within the requirements of the target product.

QLC stores four bits in each flash cell, increasing capacity while narrowing the voltage margins used to distinguish between programmed states. That places more work on the controller, error-correction system, and firmware responsible for managing endurance and reliably recovering data as the device ages.

Those trade-offs are being reassessed as AI inference changes data-centre memory hierarchies. Training has concentrated attention on high-bandwidth DRAM positioned close to accelerators, while inference can also depend on large volumes of model weights, key-value cache data, retrieval databases, and other information that is uneconomic to hold entirely in the most expensive memory tier.

Sandisk expects enterprise data-centre flash demand to grow substantially as those workloads increase. Its Investor Day material puts the total addressable market for enterprise data-centre flash at 1.2 zettabytes by 2030, although the eventual volume will depend on AI architecture, model design, accelerator memory capacity, and the distribution of data between DRAM, flash, and other storage tiers.

High Bandwidth Flash is part of that strategy. Sandisk and SK hynix have already published an open HBF interface specification for a stacked NAND tier using UCIe, while the Investor Day announcement places that technology inside Sandisk’s wider NAND and commercial roadmap rather than presenting a new interface specification.

The concept attempts to position flash closer to processors than conventional storage while retaining the capacity and cost characteristics associated with NAND. Its usefulness will depend not only on interface bandwidth but also on controller behaviour, package thermals, endurance, latency, power, and the yield involved in building dense flash stacks.

Sandisk is changing the commercial model around that manufacturing investment at the same time. The company has signed what it calls New Business Model agreements with eight customers, incorporating committed volumes, contractual minimum financial guarantees, and structured pricing mechanisms.

Those agreements represent approximately 50% of expected bit volume in fiscal 2027 and about two-thirds in fiscal 2028. Longer demand visibility can give a memory manufacturer a firmer basis for deciding when to ramp a new NAND generation and how much fabrication and packaging capacity should be committed to it.

That matters because memory manufacturing has repeatedly suffered from periods in which capacity expansion outruns demand. NAND requires large capital investment, yet additional bits entering the market can push selling prices down rapidly when several suppliers expand at the same point in the cycle.

Contracted volumes do not remove that market risk, but they can reduce uncertainty around a portion of future production. From an engineering perspective, they also help determine which process derivatives and package formats warrant development resources because the manufacturer has a clearer view of the customers expected to use them.

The AI storage market remains difficult to forecast over several years. Accelerator architectures will evolve, larger local memories can change external storage traffic, model compression may reduce some capacity requirements, and emerging memory technologies may compete for particular positions in the hierarchy.

Sandisk is responding by making the underlying NAND technology more adaptable rather than betting on one product format. Bonded CMOS creates additional options for combining array and control technologies, later BiCS generations increase density, and HBF attempts to place selected flash closer to AI compute.

The roadmap consequently links device physics, packaging, interfaces, and capacity planning more closely than a conventional NAND-generation announcement. For electronics designers, the significant change is that flash is being engineered for several positions in the AI memory hierarchy rather than treated only as bulk storage sitting behind the server’s main compute and memory subsystem.