Silanna integrates DSP into miniature data converters

Silanna has added integrated digital signal processing to its Plural Nano analogue-to-digital converter family, allowing selected signal-conditioning functions to operate within the converter rather than requiring separate downstream processing hardware.

Introduced on 11 November 2026, the Plural Nano DSP range extends the miniature converters launched earlier in the month. The additional functions include decimation, digital down-conversion, interleaving, and in-phase/quadrature mismatch correction.

Silanna is initially offering 24 configurations incorporating the DSP functions, with 12-, 14-, and 16-bit conversion and sampling rates from 5 to 250 million samples per second. The devices are intended for compact instrumentation, communications, industrial sensing, and other signal acquisition systems.

An analogue-to-digital converter samples a continuously varying electrical signal and represents its amplitude numerically. The available resolution determines the number of discrete output levels, while the sampling frequency establishes how often the input is measured.

Many acquisition systems then pass the resulting samples to an FPGA, processor, or dedicated signal-processing device. That hardware may perform filtering, frequency conversion, channel correction, and other operations before the information can be used by the application.

Moving selected operations into the converter changes the partitioning of the signal chain. Instead of transmitting the complete unprocessed sample stream to another device, the ADC can perform specified transformations before delivering the resulting digital information.

Decimation is one such operation. A converter may initially sample a signal at a relatively high rate, even though the application ultimately requires information over a narrower frequency range. Appropriate digital filtering followed by a reduction in sampling rate can produce a lower-bandwidth data stream while retaining the relevant signal content.

The filtering stage is essential because simply discarding samples can cause unwanted frequency components to appear within the output bandwidth. This effect, known as aliasing, can distort the information that the receiving processor is intended to analyse.

Performing decimation inside the ADC can reduce the data rate presented to downstream circuitry. The benefit depends on the original sampling frequency, the selected decimation ratio, and the bandwidth required by the application.

Digital down-conversion performs a different function, translating a selected portion of the sampled frequency spectrum towards a lower frequency. The resulting signal can then be filtered and processed without retaining the entire original acquisition bandwidth.

This is useful in radio receivers and measurement equipment where a relatively narrow signal must be extracted from a wider sampled spectrum. The processing arrangement determines which frequency range is retained and how much unwanted information is rejected.

Integrating digital down-conversion with the converter can reduce the number of operations implemented in external programmable logic. However, the receiver may still require additional processing for demodulation, synchronisation, data interpretation, or communication with other system components.

Silanna has also incorporated interleaving functions and IQ mismatch correction. Interleaving can combine data from multiple acquisition paths to achieve a required sampling arrangement, while channel differences can introduce errors if their timing, gain, or offset characteristics are not adequately controlled.

IQ mismatch occurs when the in-phase and quadrature components used to represent a signal do not maintain their intended amplitude and phase relationship. The resulting imbalance can introduce unwanted spectral components and reduce the accuracy of subsequent signal processing.

Correcting these effects within the converter may simplify downstream circuitry, particularly where the acquisition system would otherwise require programmable logic to perform the same operations. The extent of the saving will depend on which functions are already provided by the ADC and which remain necessary elsewhere.

Silanna states that the integrated DSP can substantially reduce, or in some cases eliminate, the need for a downstream FPGA. That result is application-dependent and should not be interpreted as a universal replacement for programmable logic.

An FPGA may still be required to aggregate multiple channels, implement high-speed communications, perform additional mathematical operations, or provide deterministic control functions. The new devices principally change where initial signal conditioning and correction take place.

The DSP-equipped converters retain the compact package options introduced with the original Plural Nano family. Selected single-channel and dual-channel devices use packages measuring 3.4 × 3.4 mm, while the larger dual-channel configurations occupy 3.7 × 3.7 mm.

Silanna claims package area reductions of approximately 83% and 86% respectively compared with selected competing converters operating above 125 MSa/s. The company also reports smaller area reductions against certain 125 MSa/s devices supplied in 5 × 5 mm packages.

These comparisons concern semiconductor package area rather than the complete circuit board. Actual board-space savings depend on the remaining analogue components, clock circuitry, power regulation, routing, and any external processing functions that the application still requires.

The integrated DSP introduces another potential reduction by moving processing functions into the ADC package. The combined benefit could be greater than the package saving alone where an external FPGA or associated support circuitry can be removed.

The Plural Nano architecture combines a pipeline ADC core with integrated reference and clock management circuitry. It supports LVDS and CMOS output arrangements and is specified for operation between -40°C and +85°C.

These characteristics provide several interface and environmental options, but integrating more digital processing does not remove the analogue requirements of high-speed conversion. Input filtering, impedance matching, grounding, power supply noise, and clock quality continue to influence measurement performance.

Sampling clock jitter can introduce uncertainty into the instant at which a varying input signal is measured, particularly as input frequency increases. Signal conditioning performed after conversion cannot automatically recover information already degraded by the analogue acquisition process.

Additional processing also creates design decisions involving output data formats, filtering behaviour, and the configuration of the digital functions. The selected processing arrangement must preserve the information needed by the application without introducing unwanted latency or discarding useful signal content.

Silanna reports that the 24 DSP-equipped configurations bring the wider Plural Nano portfolio to more than 170 devices. The company is also planning additional converter resolutions, extending a platform that uses a configurable semiconductor architecture to support different product specifications.

The Plural Nano family and associated evaluation kits are available through authorised distributors, with technical information and sample enquiries handled through Silanna's product channels. The manufacturer's announcement does not establish measured power savings or cost reductions for a particular completed acquisition system.

The DSP variants provide another design option for compact electronic equipment requiring high-speed data conversion and initial digital processing. Their board-level benefit will depend on whether the integrated functions can replace external processing resources while satisfying the application's bandwidth, accuracy, and timing requirements.