Socionext applies Cadence AI to 3nm physical design

Socionext is extending its use of artificial intelligence from front-end chip development into physical design, working with Cadence to apply the InnoStack AI Super Agent to a large-scale system-on-chip using a 3 nm manufacturing process.

The collaboration brings AI agents into tasks associated with arranging circuit structures, examining timing, and applying established engineering procedures during physical implementation. Socionext is combining Cadence software with internal design knowledge, allowing parts of its existing methods to be reused across projects instead of remaining confined to individual engineers or project teams.

Physical design follows the logical definition and verification of a semiconductor circuit. The design must be translated into an arrangement of cells, connections, and supporting structures that satisfies electrical, timing, area, and manufacturing constraints. Floorplanning establishes the broad placement of functional regions and influences subsequent routing, power distribution, and achievable operating performance.

Those decisions become more demanding as system-on-chip designs grow in complexity. Moving one large functional block can change interconnection lengths and congestion elsewhere, while attempts to improve timing may increase area or power consumption. Physical implementation consequently requires repeated assessment of alternatives rather than a single sequence of independent placement and routing operations.

At advanced process nodes, engineers must also work within restrictive manufacturing rules and evaluate signal timing, electrical loading, and power distribution. A configuration that appears promising during an early design step may fail later checks, requiring constraints or implementation decisions to be revisited. Teams therefore develop specialised scripts, review procedures, and accumulated knowledge to manage recurring problems.

Socionext has already used agentic AI in front-end development to support design and verification work, engineering analysis, and decision-making. The latest collaboration extends that effort into the physical stage, where the company is applying Cadence InnoStack to a large 3 nm device. Neither company has disclosed the processor’s customer, commercial application, or detailed implementation results.

The InnoStack AI Super Agent provides an environment in which AI agents can be connected with electronic design automation software and project-specific workflows. Socionext intends to use that framework to make its own engineering procedures available during practical design tasks, rather than relying only on general-purpose model responses.

Retrieval-augmented generation allows an agent to obtain relevant information from an approved knowledge base when processing a task. In this setting, that information might include internal methodology documents, established design practices, or guidance on how a particular review should be conducted. The value depends on the completeness and accuracy of the underlying information, which still requires engineering oversight.

Model Context Protocol support provides mechanisms through which agents can connect with tools and other relevant resources. Socionext also refers to customised AI skills, enabling particular engineering operations to be expressed in a form that can be reused. Combined with the agent framework, these functions are intended to reduce repeated manual coordination and make technical methods more consistent between projects.

The companies identify floorplanning and customised timing analysis checks among the current and intended areas of application. Future checklist automation is also under consideration. These activities differ in technical scope: floorplanning can change the physical arrangement of a circuit, while timing checks evaluate whether defined electrical and operating constraints have been satisfied.

An automated timing review requires access to reliable constraints and the correct design state. A missed or incorrectly interpreted exception can produce misleading results, just as a floorplanning suggestion must be evaluated against routing congestion, power integrity, and the manufacturing rules of the chosen process. Agent coordination cannot remove the requirement for established EDA checks and final engineering signoff.

The immediate programme therefore centres on the integration of reusable company knowledge with advanced design tools. Socionext has not claimed that an AI agent can independently complete physical implementation, nor has it released a measured comparison of design quality or turnaround time from the 3 nm project.

Hisato Yoshida, president and chief operating officer of Socionext, said the company expects overall productivity gains of up to five times through Cadence’s agentic workflow. This is a forward-looking expectation, not a result verified on the currently described chip or across a representative set of completed projects.

Cadence is presenting InnoStack as an open, extensible framework that can incorporate a customer’s proprietary methods. Chip developers accumulate specialist scripts, signoff procedures, and process knowledge over successive projects. Reusing these methods across teams may reduce repeated development work, but the underlying instructions must be maintained as tools, design rules, and manufacturing technologies change.

Socionext plans to connect its front-end AI initiatives with the physical design programme and extend the resulting capabilities to additional system-on-chip projects. It is also developing custom agents and engineering assistants to support that expansion. Neither company has published completed-project measurements establishing the resulting productivity or quality improvements. Subsequent deployments will need to demonstrate that the workflows can be reused while preserving the verification and signoff controls required for commercial silicon.