IN Brief:
- STM32H7P combines a 520 MHz Cortex-M7 with a Hardware Signal Processor and Neural-ART neural accelerator.
- The NPU delivers up to 85 GOPS, while the signal processor accelerates operations including fast Fourier transforms.
- OEM sampling is under way, with production and development boards planned for January 2027.
STMicroelectronics has expanded its STM32H7 microcontroller range with the STM32H7P family, introducing dedicated digital signal processing and neural-network acceleration alongside a 520 MHz Arm Cortex-M7 processor for industrial control and embedded computing applications.
The architecture incorporates ST’s Hardware Signal Processor (HSP) and Neural-ART Neural Processing Unit (NPU), allowing selected mathematical and machine-learning workloads to execute independently of the main processor. The devices are intended for applications including digital power conversion, motor control, industrial sensing, condition monitoring, and equipment incorporating local AI inference.
ST specifies a Cortex-M7 performance score of 2,773 CoreMark, with the integrated NPU capable of delivering up to 85 billion operations per second. Those figures describe different aspects of the processing architecture and should not be combined into a single measure of application performance.
The Hardware Signal Processor is designed to accelerate matrix, vector, and other digital signal processing operations. These calculations are common in equipment that converts measurements into control decisions, including motor drives, power supplies, vibration monitoring systems, and industrial instruments.
Digital filtering can be used to isolate relevant frequencies or reduce unwanted measurement noise, while transforms allow sampled signals to be examined in the frequency domain. Such operations may need to run repeatedly at defined intervals, placing a sustained computational load on a microcontroller that must also operate its communications and control peripherals.
A fast Fourier transform converts a sequence of sampled values into information about their frequency components. The algorithm involves repeated mathematical operations and memory accesses, making its execution time sensitive to the processing architecture and the size of the input dataset.
ST states that the HSP can complete FFT operations up to five times faster than a software implementation running on the Cortex-M7. This comparison relates to the evaluated workloads; acceleration will vary according to the algorithm, data representation, memory arrangement, and other implementation details.
Moving these calculations into dedicated hardware can release processor capacity for other tasks. It may also reduce the need for an external digital signal processor in designs where the integrated acceleration resources provide sufficient performance and support the required mathematical operations.
The Neural-ART NPU addresses a different part of the embedded computing workload. Neural-network inference uses model parameters and incoming data to calculate results such as classifications, estimates, or anomaly indicators. Repeated multiplication and accumulation account for a substantial proportion of the computation in many inference architectures.
Dedicated neural processing hardware can perform supported operations more efficiently than conventional sequential processor instructions. However, the achievable acceleration depends on the model’s structure, numerical precision, memory requirements, and the extent to which its operations can be executed by the available hardware.
ST reports an inference speed improvement of 40 times for its AI-based arc-fault circuit interrupter model used in photovoltaic inverter safety applications. The company also reports improvements of 20 times for an anomaly detection model and 15 times for a battery management model.
These are supplier-reported comparisons against software running on the Cortex-M7. They do not establish a universal performance improvement for every neural network, nor do they independently demonstrate improved safety performance in a completed photovoltaic or battery system.
In industrial equipment, inference latency can affect how analytical functions are integrated with time-sensitive control. A monitoring algorithm may need to process incoming measurements while the main controller continues executing periodic tasks associated with switching, motor operation, or communications.
Keeping these workloads separate can reduce competition for processor time, although memory transfers, peripheral access, and other shared resources must still be considered. The completed system must be evaluated against its actual timing requirements rather than relying solely on the peak throughput of an accelerator.
ST has increased the tightly coupled memory available within the STM32H7P architecture, providing up to 320 KB. This memory supports rapid and predictable access to selected instructions and data, avoiding some of the timing variation associated with cache misses and slower memory interfaces.
The devices also provide up to 2 MB of embedded Flash for software storage. Larger on-chip memory can accommodate more extensive application code and processing libraries without requiring every software component to be stored externally.
Memory capacity nevertheless remains a constraint for embedded AI. Neural-network parameters, activation buffers, sensor data, and application software must fit within the available storage and working memory, or be managed through a suitable external memory architecture.
STM32H7P also incorporates advanced analogue peripherals and timers derived from ST’s newly introduced STM32G5 mixed-signal family. Analogue-to-digital conversion, digital-to-analogue conversion, comparators, and precision timing functions provide interfaces for control systems that interact directly with electrical and electromechanical equipment.
The two microcontroller families address different processing requirements. STM32G5 concentrates on precision mixed-signal control and power conversion, while STM32H7P adds a higher-performance processor and dedicated accelerators for signal analysis and neural inference.
Software development is supported by ST’s Edge AI Suite, digital signal processing libraries, and motor control software. The STM32H7P will also use the updated STM32Cube ecosystem, including STM32CubeMX2 configuration tools and the HAL2 hardware abstraction layer.
Industrial temperature requirements have been included in the product design. ST specifies operation at ambient temperatures up to 125°C, with exposed-pad LQFP packaging options intended to improve heat dissipation. Actual operating margins will depend on the selected package, processor activity, ambient conditions, and PCB thermal design.
The new devices are sampling with OEM customers, with production scheduled for January 2027. ST has announced pricing starting at $4.43 for a device with 1 MB of Flash in an LQFP100 package at quantities of 10,000 units.
Evaluation hardware, including the NUCLEO-H7P5II board and STM32H7P5IDK Discovery kit, is also expected in January. These platforms will provide access to the processing architecture and development tools for evaluating signal-processing performance, inference workloads, and the timing behaviour of complete embedded applications.
