Synopsys expands European chip design access

Synopsys has agreed to provide electronic design automation (EDA) software through the European Chips Design Platform (EuroCDP), expanding access to semiconductor development tools for startups, small and medium-sized enterprises, and research teams working on new integrated circuits.

The agreement with the European Chips Joint Undertaking (Chips JU), confirmed on 4 November, covers digital semiconductor design, analogue and mixed-signal circuits, and photonic integrated circuits. Participants will be able to access technologies used in commercial chip development through a platform intended to reduce the technical and financial barriers associated with establishing semiconductor design operations.

Synopsys will support both Level 1 and Level 2 of the EuroCDP programme, extending its involvement from early-stage semiconductor ventures through to pre-production development. The arrangement includes digital front-end and back-end design flows, verification, and signoff tools associated with advanced systems-on-chip.

Developing an integrated circuit requires several distinct engineering stages before a design can be manufactured. Front-end development establishes the circuit architecture, describes its intended behaviour, and verifies that individual functional blocks operate according to the design requirements.

Digital synthesis converts the logical description into a gate-level implementation using cells available in the selected semiconductor manufacturing process. Engineers must then establish whether the implementation satisfies performance, power consumption, and area constraints while maintaining the functionality established during earlier verification.

Physical design introduces further requirements. Semiconductor cells must be positioned and connected within the available silicon area, with routing, clock distribution, power delivery, and timing considered as part of the completed layout. A logically correct circuit may still fail to satisfy manufacturing or operating requirements when these physical effects are taken into account.

Signoff tools assess the completed implementation against the rules and constraints associated with the intended fabrication process. Timing analysis, electrical verification, and physical design checks help identify problems that must be resolved before the design can proceed to manufacturing.

Access to production-grade tools across these stages can require a substantial investment, particularly when a semiconductor business is developing its first device. Software licensing, specialised engineering expertise, design intellectual property, and access to suitable manufacturing processes can create barriers before the first silicon prototype is produced.

EuroCDP is being established to address several of these constraints through shared access to design technologies and supporting services. Synopsys’ contribution will sit alongside the platform’s broader provision of intellectual property, training, funding support, and semiconductor prototyping resources.

Analogue and mixed-signal design forms a separate part of the agreement. These circuits process continuous electrical signals and digital information, often within the same integrated device. They are used in sensor interfaces, industrial control systems, automotive electronics, communication equipment, and power management applications.

Their development requires models that account for electrical noise, component variation, analogue signal behaviour, and the interaction between circuit blocks. Transistor-level simulation and physical layout verification are particularly important where small changes in device characteristics can affect the accuracy or stability of the completed circuit.

Photonic integrated circuits introduce another class of design requirements. Rather than relying exclusively on electrical signals, these devices manipulate light using structures manufactured on semiconductor substrates. Applications include optical communications, sensing, and interconnects used in computing infrastructure.

Optical behaviour, manufacturing tolerances, device geometry, and interactions with surrounding electronic circuitry all influence the design. Specialist photonic simulation and layout capabilities are therefore needed alongside conventional electronic design tools, particularly where optical and electrical functions must operate within a common assembly.

Synopsys is extending access to these workflows as Europe seeks to increase its semiconductor design capacity. The European Commission estimates that European chip design companies account for less than one per cent of global revenues in the sector, despite the region’s established research institutions, equipment manufacturers, and semiconductor production capabilities.

The Commission has confirmed that the European Chip Design Platform is expected to mobilise €525 million in investment. That figure applies to the broader European initiative and should not be interpreted as the value of Synopsys’ agreement or a financial contribution committed by the company.

Manufacturing capacity alone cannot establish a complete regional semiconductor ecosystem. Foundries require designs suitable for their production processes, while fabless semiconductor companies need access to process design kits, verified circuit libraries, engineering tools, and the resources required to validate their devices.

The design platform is intended to connect these activities more effectively. Its resources include design support services, intellectual property blocks, and routes towards manufacturing capacity, potentially allowing smaller companies to undertake development stages that would otherwise require substantial independent investment.

Synopsys already works with several European semiconductor businesses, including Axelera AI, Openchip, and SiPearl. Axelera has used the company’s digital implementation and verification technologies in the development of its Metis and Europa AI processing units, alongside power integrity technology from Ansys, now part of Synopsys.

The new arrangement broadens the potential route through which similar development capabilities can be accessed. However, the announcement does not establish individual licensing prices, eligibility decisions, or the amount of engineering assistance available to each participating organisation.

Successful chip development will also depend on access to compatible manufacturing processes and the resources required for physical verification, test development, and silicon validation. The availability of design software reduces one barrier but does not replace the engineering and financial work needed to manufacture and qualify an integrated circuit.

EuroCDP’s next operational milestones will determine how participating companies gain access to the tools, design support, and fabrication resources, and how those services connect early-stage semiconductor projects with commercially manufacturable devices.