IN Brief:
- Toshiba reduced threshold-voltage drift by approximately 50% compared with commercial trench-gate SiC MOSFETs in its tests.
- The gate-formation process suppresses interface charge traps while maintaining the low on-resistance associated with the trench structure.
- Toshiba has applied the technique to its 1200V TW007D120E, which entered test-sample shipment in May.
Toshiba Electronic Devices & Storage has developed a gate-formation process for trench-gate silicon carbide MOSFETs that reduces threshold-voltage drift by approximately 50% compared with commercial trench devices while maintaining low on-resistance.
The process targets a reliability issue created by the gate structure used in high-performance SiC power devices. Trench geometries can increase channel density and lower device resistance, but the gate oxide and semiconductor interface can also experience charge trapping under repeated electrical stress.
Threshold voltage determines the gate voltage at which a MOSFET begins to conduct. Movement in that threshold over the operating life can alter switching margins, increase conduction loss, and complicate gate-drive design, particularly when a converter is expected to operate for years under repeated high-frequency switching.
Toshiba investigated the relationship between the interface treatment used during gate-oxide formation and the amount of threshold shift produced by alternating positive and negative gate stress. Its measurements showed substantial differences according to nitridation and other processing conditions.
The company attributes part of the drift to charge traps created around the gate-oxide interface. By adjusting the interface treatment and associated process parameters, Toshiba established a gate-formation sequence intended to suppress those traps without losing the low on-resistance that makes the trench architecture attractive.
Testing included repeated positive and negative gate bias at switching frequencies in the hundreds of kilohertz. One published condition applied +25V and -10V gate stress at 500kHz for 1011 cycles, while comparison measurements against commercial trench-gate devices used 400kHz operation over the same number of cycles.
Under those conditions, Toshiba reported threshold-voltage drift at approximately half the level measured in commercially available trench-gate SiC MOSFETs used for comparison. The figures are Toshiba test results rather than an independent industry benchmark, but they establish the process change against a defined electrical stress regime.
The technique has already been applied to the TW007D120E, a 1200V trench-gate SiC MOSFET that began test-sample shipment in May. The device uses a QDPAK package with top-side cooling and is intended for high-density power conversion.
Published electrical data for the TW007D120E includes 7mΩ typical drain-source on-resistance at a 15V gate drive, a 172A DC drain-current rating at a 25°C case temperature, and 33nC typical gate-drain charge. Target applications include AI data-centre power systems, renewable energy conversion, uninterruptible power supplies, energy storage, EV charging, and industrial drives.
Those systems increasingly push power semiconductors towards higher switching frequencies and greater power density. SiC can reduce switching and conduction losses compared with conventional silicon in appropriate converter architectures, but device reliability still has to match the long service life expected in industrial and infrastructure equipment.
Gate stability is particularly relevant because changes at the device interface can accumulate while every individual switching event appears electrically normal. A converter designed around a particular threshold margin may therefore see its operating window change gradually rather than fail through one catastrophic event.
Trench structures sharpen the trade-off. They reduce resistance by increasing effective channel area and altering current flow through the device, but they also expose different parts of the gate oxide to strong electric fields. Process optimisation has to preserve the electrical benefit while controlling the interface behaviour introduced by the geometry.
Toshiba presented the work at the 23rd International Conference on Silicon Carbide and Related Materials in Yokohama. The programme was supported by Japan’s New Energy and Industrial Technology Development Organization, and the company plans to extend the gate-process technique to further SiC MOSFETs.
No wider product family, mass-production date, automotive qualification programme, or production-volume target has yet been announced for the revised process. The TW007D120E remains the disclosed test vehicle, allowing Toshiba to combine an existing 1200V trench device with the new interface treatment while the reliability data develops.
The next stage will be broader qualification across production variation, temperature, switching conditions, and operating lifetime. The laboratory result establishes that interface processing can materially reduce threshold drift; production deployment will determine whether that improvement can be retained consistently across a commercial SiC device range.
