UC Berkeley joins Applied semiconductor research centre

Applied Materials is bringing the University of California, Berkeley into its EPIC Center as a research collaborator, giving university teams access to industry-scale semiconductor process equipment alongside the company’s engineers.

The collaboration is intended to shorten the path between materials and device research carried out in academia and the manufacturing conditions required to turn that work into commercial semiconductor processes. UC Berkeley faculty and students will use the Silicon Valley facility for research tied to future computing and chip technologies, including areas relevant to AI hardware.

That intermediate stage between laboratory research and high-volume manufacturing is one of the more difficult parts of semiconductor development. A new material or process can demonstrate promising electrical behaviour on university equipment yet still fail once it has to meet requirements for wafer uniformity, contamination control, defectivity, tool repeatability, throughput, and integration with the process steps around it.

Applied’s EPIC model is designed to expose research to those constraints earlier. Rather than waiting until a concept is mature enough to enter a chipmaker’s development line, researchers can work with equipment closer to the scale and operating conditions used in commercial semiconductor manufacturing.

The centre’s name — Equipment and Process Innovation and Commercialization — reflects that focus. Applied says the facility is intended to bring equipment development, materials engineering, process integration, customers, and research organisations into a common environment, reducing the distance between an early experiment and a process that can be evaluated for production.

UC Berkeley is a logical partner because semiconductor research has been a long-running part of the university’s engineering work. Applied points to Berkeley’s role in developments including the SPICE circuit simulator and the FinFET transistor architecture, both of which eventually became deeply embedded in commercial semiconductor design and manufacturing.

The historical examples are useful because they show how different the route to impact can be. SPICE became a design tool used throughout electronics engineering, while the FinFET changed transistor structure at the process level. Neither moved from university research to industrial ubiquity simply because the underlying idea worked; adoption depended on years of development, validation, integration, and commercial implementation.

The same problem has become harder as leading semiconductor devices rely on increasingly complex interactions between materials, patterning, deposition, etch, metrology, interconnects, packaging, and device architecture. A change intended to improve one electrical characteristic can alter thermal behaviour, reliability, yield, or the manufacturability of later process steps.

Equipment suppliers sit in an unusual position in that chain. Their tools are used across multiple chipmakers, giving them detailed knowledge of process windows and manufacturing requirements without tying every research activity to a single finished processor or memory product. An academic collaboration at equipment level can therefore test whether a promising concept survives contact with manufacturing constraints before a fab commits scarce development capacity.

The approach does not guarantee rapid commercialisation. A process still has to deliver enough performance, yield, reliability, and economic value to justify insertion into a production flow, and semiconductor manufacturers are understandably reluctant to disturb a stable process for marginal gains. EPIC instead provides a more representative environment in which some of those objections can be identified earlier.

Applied has previously said the EPIC Center represents its largest US investment in advanced semiconductor equipment research and development. The facility is on track to become operational in 2026, with Berkeley joining a broader collaboration model intended to include universities, chipmakers, and technology partners.

For electronics designers, the eventual output will be several layers removed from the board or system. Materials and process innovations developed in facilities such as EPIC determine transistor performance, power efficiency, interconnect density, and manufacturing cost long before those characteristics appear in a processor, memory device, sensor, or accelerator datasheet.

The Berkeley agreement is therefore more than an academic partnership in name. Its value will be measured by whether researchers can use manufacturing-scale equipment to identify process limitations earlier, turning fewer promising laboratory results into dead ends only after they reach the expensive part of semiconductor development.