IN Brief:
- Synopsys has announced expanded IP, EDA, and system-level enablement across TSMC nodes and packaging technologies.
- The work covers N3, N2, A16, A14, 3DFabric, CoWoS, optical, electrical, and thermal analysis.
- The collaboration addresses the rising design complexity of AI and high-performance computing silicon.
Synopsys has expanded its collaboration with TSMC across silicon-proven IP, AI-powered EDA flows, and system-level enablement for advanced AI and high-performance computing designs.
The work spans TSMC’s 3nm and 2nm families, as well as A16 with Super Power Rail and A14. It includes certified design flows, interface IP, foundation IP, verification, power integrity, multi-die analysis, and co-packaged optics design enablement.
Synopsys has reported successful silicon bring-up of low-power M-PHY v6.0 IP on TSMC N2P, tape-out activity for 64G UCIe IP, and 224G IP development for next-generation AI systems. The company is also working with TSMC on AI-assisted digital, analogue, and verification flows designed to improve design productivity and quality of results.
For multi-die designs, Synopsys 3DIC Compiler supports TSMC 3DFabric technologies, including TSMC-SoIC and CoWoS for 5.5x reticle interposer sizes. The platform integrates with RedHawk-SC, RedHawk-SC Electrothermal, and Ansys HFSS software to provide analysis across thermal, power, and high-speed signal-integrity domains.
The collaboration also extends power-integrity coverage across TSMC A16 and A14, with Synopsys Totem-SC supporting analogue power integrity signoff for large N2-based designs and embedded memories. Synopsys PathFinder-SC extends multi-die electrostatic discharge signoff coverage to N2.
Co-packaged optics are also covered. The flow supports optical path simulation through Ansys Zemax OpticStudio, photonic device simulation with Ansys Lumerical, electromagnetic extraction through HFSS-IC Pro, and thermal and electrical co-simulation through RedHawk-SC Electrothermal.
Advanced silicon design now depends on more than transistor scaling. AI processors and high-performance computing devices require tightly managed interactions between compute die, memory, interconnect, packaging, power delivery, and cooling. A timing-closed digital block cannot be treated separately from the package and system environment around it.
Multi-die architectures increase that complexity. Designers must account for die-to-die signalling, thermal gradients, package parasitics, power integrity, ESD, mechanical assembly, and manufacturability before tape-out. Errors discovered late in that chain can be expensive and difficult to correct.
AI-assisted EDA flows are being introduced to reduce manual iteration in placement, timing closure, analogue verification, and signoff. The use of agentic run assistance in Fusion Compiler on TSMC A14 shows how automation is being applied directly to advanced-node design closure rather than confined to early-stage exploration.
Synopsys and TSMC are tying IP, EDA, 3D packaging, photonics, and multiphysics analysis into a more continuous design environment. That integration is becoming essential for AI silicon, where bandwidth, power, thermal density, and package architecture now determine whether compute performance can be used effectively at system level.
