IN Brief:
- Siemens’ Veloce Strato CS platform was used to verify Arm’s AGI CPU from subsystem to full-system level.
- The CPU is built on the Arm Neoverse CSS V3 platform for agentic AI and cloud data centre deployment.
- The work highlights rising verification pressure around AI compute platforms, coherent interconnects, firmware, and pre-silicon software readiness.
Siemens has collaborated with Arm to support verification of the Arm AGI CPU, using the Veloce Strato CS hardware-assisted verification platform to validate a processor design for next-generation agentic AI workloads.
The Arm AGI CPU is built on the Arm Neoverse Compute Subsystem V3 platform and is intended for high-performance, energy-efficient compute in agentic AI and cloud data centre deployments. Siemens’ Veloce Strato CS platform was used to support verification from subsystem through to full-system level, covering performance, latency, and power targets before tape-out.
The verification work used Siemens hardware-assisted verification, emulation, and prototyping technologies to address the scale of Arm’s Neoverse V-series Compute Subsystem. The design incorporates high-speed interconnects, PCIe Gen6, NVMe, and CXL, creating a verification environment that extends beyond traditional software-only EDA flows.
Siemens’ Veloce proFPGA CS prototyping platform was also used to accelerate pre-silicon software development. FPGA-based prototypes allow software teams to begin driver development, system bring-up, and validation before production silicon is available, reducing the risk of firmware and software readiness becoming the critical path.
Processor development for AI infrastructure now depends on full-platform validation rather than isolated block closure. CPUs, accelerators, memory controllers, coherent fabrics, chiplet interfaces, storage links, and high-speed I/O have to operate together under workload conditions that resemble production deployment. Verification has to prove that the complete platform behaves predictably, not only that individual IP blocks meet their specifications.
Agentic AI workloads add further pressure. These systems can involve long-running tasks, complex scheduling, persistent context, heavy memory traffic, and close interaction between compute, storage, and networking resources. Processor performance is therefore tied to latency, power efficiency, bandwidth, software orchestration, and system stability under sustained load.
Hardware-assisted verification has become central to that process because simulation alone cannot run enough system-level software or workload depth at practical speeds. Emulation and prototyping allow engineering teams to validate firmware, drivers, boot flows, operating systems, interface behaviour, and performance-sensitive workloads before silicon returns from the fab.
For hyperscale and AI infrastructure designs, late-stage errors carry high cost. A problem in coherency, link negotiation, power sequencing, or firmware interaction can delay deployment even if the core processor logic is sound. Large AI compute platforms also bring tighter schedules, as cloud operators and silicon developers race to bring new architectures into production.
The availability of similar Veloce Strato CS workflows to Arm licensees and ecosystem partners is also relevant for custom silicon programmes based on Arm compute subsystems. Companies building infrastructure processors around Arm platforms face many of the same barriers: large design size, complex interconnects, software dependencies, and pressure to validate complete systems before tape-out.
The Siemens and Arm collaboration shows how processor verification is moving towards system-level evidence at scale. The processor, firmware, interconnect, and software stack increasingly have to be treated as one engineering problem before silicon reaches manufacturing.
