IN Brief:
- More than 120 students from ten UK universities designed and submitted ASICs for fabrication.
- The workshop used Tiny Tapeout’s open-source, multi-project wafer approach.
- The programme addresses barriers around EDA access, fabrication cost, and practical semiconductor design training.
The University of Sheffield has hosted a major Tiny Tapeout workshop, giving more than 120 students from ten UK universities the opportunity to design and submit their own microchips for fabrication.
The workshop was run through the School of Electrical and Electronic Engineering and supported by EnSilica and other semiconductor industry sponsors. It used the Tiny Tapeout framework, an open-source, multi-project wafer approach that enables low-cost fabrication of application-specific integrated circuit designs.
Participants progressed from initial concept to chip design and tape-out within a single afternoon. The event is believed to be the largest Tiny Tapeout workshop and mass tape-out cohort to date globally, with each student able to submit an individual design as part of a shared fabrication run.
The workshop was open to students with no prior chip design experience. It introduced digital logic fundamentals before guiding participants through the process of preparing a design for silicon. The chips are now heading to manufacture, with students expected to return later in the year to test their designs on real silicon.
The programme was supported by Sheffield Hardware and Reconfigurable Computing, known as SHaRC, a student-led community that helped deliver the workshop and scale participation.
Practical chip design experience remains difficult to access in many university settings. Students may study digital electronics, computer architecture, embedded systems, and HDL-based design, but the cost and complexity of EDA tools, foundry access, and fabrication have often kept real tape-out experience outside standard teaching routes.
Tiny Tapeout lowers that barrier by combining open-source tooling with shared fabrication. The multi-project wafer model allows many small designs to be manufactured together, reducing cost while still exposing students to the disciplines required for silicon submission. Designs have to be constrained, checked, and prepared for a manufacturing flow, making the exercise more demanding than a simulation-only assignment.
That distinction is important for early-stage engineers. Preparing a design for fabrication introduces constraints around area, timing, I/O, verification, layout, and test that are easy to miss when projects remain on screen. When fabricated silicon returns, students also encounter bring-up, measurement, debugging, and the reality that a physical device may reveal issues not visible in the design environment.
The UK semiconductor sector has specific strengths in design services, compound semiconductors, specialist IP, automotive electronics, sensing, communications, photonics, and advanced packaging. These areas depend on engineers who understand how digital logic, embedded systems, interfaces, packaging, test, and manufacturing interact. A broader base of graduates with tape-out experience would support companies working across ASIC design, FPGA prototyping, embedded platforms, and hardware security.
Programmes such as Sheffield’s workshop also help make chip design more visible. Semiconductor engineering can appear distant from undergraduate electronics because fabrication is often hidden behind commercial toolchains and specialist facilities. Giving students a route from concept to silicon makes the discipline tangible and gives employers a stronger foundation to build on when recruiting into design and verification roles.
The finished student chips will give participants a second phase of learning when the devices return for testing. That loop from design to fabrication to measurement is central to semiconductor engineering, and it is still rare enough in education to make a single afternoon tape-out a useful intervention for the UK talent pipeline.
