IN Brief:
- ST54M combines NFC, eSIM, embedded secure element, and post-quantum cryptography acceleration on a single die.
- The device supports ML-KEM and ML-DSA algorithm families, with certification and production targeted for July 2026.
- Hardware security is moving deeper into connected products as identity, payment, and authentication services converge.
STMicroelectronics has introduced ST54M, a single-die secure mobile chip that combines an NFC controller, embedded secure element, embedded SIM, and post-quantum cryptography hardware accelerator.
The device is designed for products that handle payments, identity credentials, transit ticketing, access control, operator services, and digital car keys. Several security functions have been brought into one package, reducing the number of discrete elements required in space-constrained designs while bringing cryptographic migration into the component selection process.
ST54M supports the ML-KEM and ML-DSA algorithm families, which form part of the post-quantum cryptography standardisation landscape. The device also includes up to 4.5MB of non-volatile memory, 16KB of RAM, ISO/IEC 14443 Type A and B support, FeliCa, MIFARE, and a WLCSP90 package.
Power integration is also built into the package, with a DC-DC converter providing output power of up to 3W. That gives product teams more room to manage RF behaviour, antenna layout, low-power operation, and thermal limits in devices where mechanical space is already tightly controlled.
Certification and production are targeted for July 2026, with sampling available through ST sales offices. The platform has completed certification testing under Common Criteria 2022 EUCC and EMVCo, placing the device in a market where component choice is tied closely to scheme approval, attack resistance, and long field life.
Secure elements have traditionally sat inside payment, SIM, and high-value identity systems, but the boundary between mobile hardware and broader connected-device hardware is narrowing. Wearables, industrial access devices, medical authentication products, connected ticketing systems, vehicle access modules, and edge devices increasingly need trusted storage, secure execution, and authenticated transactions.
Post-quantum security also changes product planning horizons. Devices entering development now may remain in field use through the 2030s, particularly in payment, transport, access, and regulated industrial environments. Hardware acceleration can reduce latency, memory burden, and energy cost while giving manufacturers a more practical route through algorithm transition and certification.
Alongside work on logic scaling below one nanometre, security integration shows how semiconductor development is being pulled in several directions at once. Density and energy efficiency remain central, but trust functions, cryptographic agility, and certification readiness are now becoming part of the silicon roadmap rather than software additions applied later.
The integration of NFC, eSIM, secure element, and PQC acceleration affects software, firmware, service provisioning, antenna design, power management, and product qualification. Concentrating those functions in one die can simplify the physical design, although the wider system still has to preserve secure boot, lifecycle management, identity handling, and update pathways.
ST54M reflects the direction of connected hardware design, where security is being pulled closer to the root of the system. Credentials, transactions, access control, and authenticated services all depend on silicon-level trust, and post-quantum readiness is now entering the component catalogue rather than waiting at the edge of the standards process.
