IN Brief:
- IBM has unveiled 0.7nm, or 7 angstrom, chip technology using a nanostack architecture.
- The approach vertically stacks and staggers transistors to extend logic scaling below 1nm.
- Advanced AI and cloud hardware are increasing pressure on logic density, SRAM scaling, and power efficiency.
IBM has unveiled sub-1 nanometre chip technology built around a new nanostack transistor architecture, extending logic scaling into the 0.7nm, or 7 angstrom, node range.
The technology uses a three-dimensional nanosheet-based structure in which transistors are vertically stacked and staggered. IBM says the approach enables greater transistor density while allowing material optimisation across the stacked layers, creating a route beyond current nanosheet architectures.
The company reports that the new chip can place nearly 100 billion transistors on a chip the size of a fingernail, close to twice the density of IBM’s 2nm chip announced in 2021. Published technical results project up to 50% more performance or 70% greater energy efficiency than IBM’s 2nm node chips, with separate VLSI 2026 work showing 40% scaling in SRAM bitcells.
That SRAM advance deserves particular attention. Logic density attracts the headline, but memory density and data movement increasingly constrain AI and cloud processors. High-bandwidth workloads require faster compute blocks, denser memory structures, lower interconnect energy, and more efficient movement of data between logic and memory. SRAM area has become a persistent limiter in advanced SoC design as cache demands rise.
IBM’s nanostack architecture is intended to move beyond current nanosheet technology by using 3D sequential integration. The structure has been experimentally validated through ultra-thin dielectric bonding in CMOS integration, dual-channel engineering capability, and functional CMOS inverter operation with expected switching performance.
The development remains a research milestone rather than a production process ready for immediate deployment. IBM sees a path to production in as early as five years, and the work will depend on manufacturing partners, lithography progress, process integration, yield, inspection, and cost control. Sub-1nm architecture only becomes industrially meaningful when it can survive the realities of wafer manufacturing and volume qualification.
The manufacturing challenge connects directly with developments already visible in Europe. AlixLabs’ atomic pitch splitting platform is moving from process concept towards equipment development, while TNO and ASML are scaling an InP photonic chip pilot line in Eindhoven. Those technologies sit in different parts of the semiconductor ecosystem, but all point to the same constraint: future electronics performance depends on process control, packaging, materials, lithography, and industrialisation being developed together.
High-NA EUV will also sit within the scaling environment. IBM and its partners are working at Albany, New York, where a high numerical aperture EUV lithography tool is expected to support future logic scaling. Such tools can improve patterning precision at smaller dimensions, but device structure, materials, deposition, etch, metrology, and thermal budgets will still determine whether a node is manufacturable.
The node number alone does not carry the full design story. Sub-1nm technologies will need design rules, standard cell libraries, SRAM compilers, EDA support, power delivery schemes, reliability models, and packaging options before they can influence commercial processors. Denser structures may also increase sensitivity to variability, thermal effects, and interconnect delays.
AI infrastructure is pushing every layer of the hardware stack, from accelerators and high-bandwidth memory to power delivery and cooling. Europe’s expanded chip policy framework keeps leading-edge logic, memory, packaging, and design inside the industrial strategy, but research milestones will still have to become qualified process flows, validated supply chains, and usable design platforms.
IBM’s nanostack work shows that transistor scaling has not ended, although it has become more complex and less dependent on simple geometric shrink. The next gains will come from stacking, materials engineering, memory scaling, lithography, and packaging moving as one system rather than as separate technology tracks.
