IN Brief:
- Movellus is making its Aeonic on-die power optimisation IP available to designers using Samsung Foundry advanced process technology.
- High-resolution telemetry and nanosecond-scale actuators are intended to manage transient power behaviour inside AI and HPC SoCs.
- The collaboration moves more power-management intelligence onto the die as advanced-node designs operate with tighter voltage and thermal margins.
Movellus is bringing its Aeonic on-die power optimisation and telemetry IP into Samsung Foundry’s advanced-node ecosystem, giving AI and high-performance computing SoC designers another route to manage short-duration power events closer to the circuitry that creates them.
The collaboration makes Aeonic available through Samsung’s Advanced Foundry Ecosystem, or SAFE. Movellus combines high-resolution on-die telemetry with nanosecond-scale actuators intended to identify and respond to transient voltage and power behaviour while the processor is operating, rather than relying entirely on board-level regulation or slower firmware control.
That distinction becomes important as high-performance processors move rapidly between different workloads. Large logic blocks can switch from relatively light activity to heavy computation in very short periods, producing sudden changes in current demand through the package and power-delivery network. A brief voltage droop may be enough to compromise timing even when average supply conditions appear comfortably within specification.
Designers traditionally protect against those conditions with voltage margin, frequency limits, or wider guard bands across process, voltage, and temperature variation. The approach is robust, but it also gives away part of the performance or efficiency gained from moving to a more advanced process node.
Movellus is attempting to recover some of that margin by measuring conditions locally and reacting at silicon timescales. Its Aeonic family uses digitally implemented sensing, clocking, and control functions that can be integrated alongside the surrounding logic, allowing power-management behaviour to be tailored more closely to the SoC rather than treated as a separate board-level function.
Samsung has previously identified its 4nm foundry technology as one implementation point for Aeonic, while SAFE provides the commercial and technical framework for customers to adopt supported IP within Samsung process flows. For a chip designer, foundry ecosystem support matters because the usefulness of any IP block depends on characterisation, implementation data, verification support, and predictable behaviour on the process used for production.
The problem is particularly acute in AI accelerators, CPUs, network processors, and similar high-performance devices. Frequency, supply voltage, switching activity, and temperature are tightly coupled, while the workload may be distributed unevenly across cores and accelerator blocks. Designing every region around the same worst-case condition can leave performance unused elsewhere on the die.
Fine-grained telemetry provides an alternative if the measurements are sufficiently accurate and the control loop responds quickly enough. Different regions can operate closer to their available margin, while transient events can be detected before a slower system-level controller would normally respond.
The attraction comes with a substantial verification burden. The sensing and actuation mechanisms have to remain predictable across manufacturing variation, ageing, temperature, changing workloads, and the full set of operating corners already used during SoC sign-off. A control mechanism intended to reduce guard bands is of little use if uncertainty in the controller simply requires another guard band around it.
Telemetry can also provide information beyond the immediate control loop. On-die measurements give system developers a more detailed view of how workloads interact with voltage and thermal behaviour, potentially supporting characterisation, fault analysis, and longer-term power management once the device is deployed.
That places Aeonic within a broader change in processor power architecture. External voltage regulators and package-level delivery remain essential, but control is increasingly distributed between the board, package, silicon, firmware, and workload scheduler because the electrical margins separating those layers have narrowed.
The Samsung collaboration does not amount to a processor design win by itself. Customers still have to select the IP, integrate it, verify it, and show that the additional sensing and control circuitry produces enough performance or efficiency benefit to justify the implementation effort.
Advanced process nodes have made transistor density easier to increase than usable power density. Movellus is addressing the less marketable part of that equation — keeping expensive silicon close to its intended operating point without solving every transient by adding more voltage margin.
