IN Brief:
- CEA-Leti is treating 3D integration as a system architecture decision rather than a final packaging step.
- Fine pitch die to wafer bonding could shorten connections between processors, memory, and specialised chiplets.
- Thermal density, power delivery, alignment, yield, and test remain central barriers to volume deployment.
CEA-Leti is advancing a 3D integration programme that brings memory, processing, power delivery, cooling, and test into one architectural framework for future artificial intelligence hardware.
At the centre of the work is die to wafer hybrid bonding with interconnect pitches down to one micrometre, which shortens the electrical paths between separate dies while increasing the number of connections available within a given area. The institute has demonstrated a functional test vehicle containing approximately 100,000 links, establishing the process steps needed for denser multi die assemblies.
Separate logic, cache, memory, analogue interfaces, and specialised accelerators can be manufactured on process technologies chosen for their individual functions, then connected vertically rather than combined on one large system on chip. Such partitioning can improve yield and design flexibility, although it transfers much of the engineering difficulty into bonding, power distribution, thermal control, and system test.
Electrical characterisation of daisy chain structures produced the expected performance and yield at pitches from five to two micrometres. At one micrometre, alignment accuracy in existing bonding tools became the limiting factor, prompting a second generation test vehicle intended to use equipment with 0.5 micrometre alignment capability and pursue a 0.5 micrometre interconnect pitch.
Further development will combine the bonding process with high density through silicon vias, through oxide vias, and controlled filling of the gaps between stacked dies. Together, those elements create vertical electrical paths through reconstructed wafers while maintaining the flatness and mechanical stability required for subsequent processing.
Chemical mechanical planarisation is especially important after the spaces between dies have been filled, since later bonding and interconnect steps depend on exceptionally uniform surfaces. Local topography or misalignment can interrupt copper connections across the hybrid interface, turning small process variations into failures across densely connected structures.
Closer integration concentrates competing constraints
Reducing the distance between memory and logic lowers both latency and the energy consumed in moving each bit, particularly when wide parallel interfaces replace a smaller number of very fast serial links. AI accelerators benefit directly because data movement through the memory hierarchy can consume substantial power even before arithmetic operations begin.
The same objective is driving work on ferroelectric memory integrated more closely with AI processing, where denser non volatile storage could reduce repeated transfers between separate memory and compute devices. Hybrid bonding extends that principle across several dies, allowing different memory types and processing functions to occupy neighbouring layers.
Vertical proximity, however, intensifies thermal interaction. A processor with rapidly changing power density may sit above or below temperature sensitive memory, while the reduced package footprint leaves less surface area through which heat can escape. Die placement, workload scheduling, thermal interface materials, heat spreaders, and liquid cooling can no longer be treated as decisions made after the electrical architecture has been fixed.
Power delivery creates a related difficulty because stacked devices concentrate current demand within a smaller area. Conventional packages distribute power laterally through substrates and on die networks, whereas future assemblies may require backside delivery, integrated voltage conversion, local passives, or additional power planes to control loss and voltage droop.
Yield and test economics will determine whether these structures move beyond specialist products. A defective die can reduce the value of an entire stack after several expensive components have been bonded, so known good die testing, access to internal nodes, temporary bonding, and repair strategies must develop alongside the physical interconnect.
Standard chiplet interfaces can broaden the supplier base, yet the shortest and most efficient connections are often tied to a particular package, foundry process, or bonding flow. Designers consequently face a choice between interoperability and maximum density, with the balance changing according to volume, performance, and expected product life.
Applications impose different limits as well. Data centre accelerators can support elaborate cooling and high package power, while automotive, aerospace, and edge systems must tolerate vibration, wider temperatures, restricted airflow, and much tighter volume constraints. A bonding process that succeeds electrically still needs an architecture suited to the environment in which the finished assembly will operate.
Advanced packaging also gives Europe an industrial route that is not confined to ownership of the smallest logic node. Bonding tools, metrology, materials, thermal engineering, power integration, and test equipment create a substantial manufacturing chain around the finished device, while research programmes such as FAMES provide shared facilities for transferring those processes towards production.
CEA-Leti’s work places those disciplines at the beginning of system development rather than at the edge of a completed processor design. As interconnect pitches fall below one micrometre, the boundaries between chip design, packaging, cooling, and manufacturing become progressively less useful.
