IN Brief:
- Imec has reported two ferroelectric memory advances aimed at future AI and data-intensive systems.
- The work covers low-voltage ferroelectric capacitors and a five-word-line vertical FeFET stack.
- Memory density, bandwidth, voltage scaling, and energy efficiency are becoming decisive constraints in advanced compute design.
Imec has demonstrated two ferroelectric memory advances aimed at future AI systems, where memory density, bandwidth, and energy efficiency are becoming harder to scale through conventional architectures alone.
The Belgian research institute presented the work at the 2026 IEEE / JSAP Symposium on VLSI Technology & Circuits, covering low-voltage ferroelectric capacitors and vertically stacked ferroelectric field-effect transistor memory cells. Both developments sit beyond mainstream DRAM and SRAM scaling, targeting memory structures able to carry higher data loads without simply increasing power consumption or die area.
The first development centres on ferroelectric capacitors operating at around 1.3V while maintaining remnant polarisation above 40 μC/cm² and endurance of at least 10¹³ cycles. Those characteristics are closely tied to future DRAM-like memories, where lower voltage operation must be balanced against reliability, charge behaviour, and process integration.
Ferroelectric materials have drawn renewed interest because they can support non-volatile behaviour while enabling lower-voltage operation. Translating that into manufacturable memory remains difficult, with scaling pressure affecting the ferroelectric layer, cell behaviour, retention, endurance, and read/write margins. Imec’s latest results show progress in reducing operating voltage without giving up the electrical characteristics needed for reliable operation.
In parallel, the institute has demonstrated a vertically stacked IGZO-based FeFET architecture with five functional word lines. Moving cells vertically increases storage density without relying only on planar shrink, bringing the approach closer to the three-dimensional direction now visible across advanced memory, NAND, logic, and packaging roadmaps. A dual-gate structure with a back gate has also been introduced to improve erase efficiency, one of the persistent obstacles in FeFET development.
The two strands of research are connected by more than material choice. Ferroelectric capacitor work can feed into FeFET optimisation, while vertical stacking techniques developed for FeFETs may support denser 3D ferroelectric capacitor arrays. Memory roadmaps now depend on this kind of integration discipline, with device physics, materials engineering, process compatibility, and array architecture increasingly interlocked.
Compute demand is amplifying that pressure. AI accelerators have pushed high-bandwidth memory, DRAM, and NAND into a more strategic position in the semiconductor market, and the recent surge in memory-linked semiconductor revenue has underlined how much system performance now depends on data movement rather than raw compute alone.
Higher accelerator counts and larger models increase the penalty attached to memory latency, bandwidth limits, and power-hungry data transfer. More compute offers diminishing returns if data cannot be supplied quickly enough, stored densely enough, or moved efficiently enough between processing units and memory arrays. The energy cost of data movement is already a major constraint in AI infrastructure, and that cost rises as training and inference workloads expand.
Three-dimensional memory architectures offer one route through the bottleneck, but they shift the burden onto process integration and reliability. Stacked cells must maintain usable behaviour across layers, interfaces, and repeated operation. Ferroelectric devices also have to demonstrate endurance and erase characteristics that can support practical system use, not only isolated test structures.
Europe’s semiconductor base has particular strength in this kind of pre-competitive integration work, where materials, device concepts, pilot-line process capability, and system-level research meet before commercial manufacturing decisions are made. Low-power memory, embedded non-volatile memory, and advanced integration are all relevant to AI systems, industrial electronics, medical devices, edge hardware, and secure connected platforms.
Imec plans further work on endurance and erase performance in FeFETs, alongside voltage scaling and reliability in ferroelectric capacitors. System-level evaluation and fully integrated 3D memory architectures are expected to follow. The research remains at an early stage, but it addresses a problem already visible in production systems: AI hardware is advancing quickly, and memory technology has to close the widening gap between compute ambition and data delivery.
