IN Brief:
- MediaTek is expanding its NVLink Fusion work as a design foundation for customers developing custom AI XPUs.
- The architecture combines NVLink scale-up connectivity, chip-to-chip links, customised HBM integration, and advanced packaging.
- NVIDIA has invested $3.5 billion in MediaTek convertible bonds as the wider engineering relationship deepens.
MediaTek is deepening its work with NVIDIA’s NVLink Fusion platform for custom AI accelerators, giving cloud and hyperscale customers a prevalidated route from differentiated XPU silicon through advanced packaging, high-bandwidth memory, and rack-scale interconnect.
The August 2026 agreement is an expansion rather than MediaTek’s first involvement with NVLink Fusion. NVIDIA named MediaTek among the platform’s initial custom-silicon partners when NVLink Fusion was introduced in 2025. The new announcement adds a broader engineering and commercial framework, including MediaTek offering the platform as a design foundation for customer XPUs and NVIDIA investing $3.5 billion in MediaTek convertible bonds.
NVLink Fusion is intended to reduce the amount of infrastructure engineering that accompanies a custom accelerator. Building the compute die is only one part of an AI system: developers also need die-to-die connectivity, HBM integration, package co-design, high-speed SerDes, thermal management, validation, and a scale-up fabric capable of linking many accelerators inside the same rack.
The platform combines an NVLink Fusion chiplet with NVLink-C2C and NVIDIA NVHBM technology. The chiplet connects a customer’s XPU to NVIDIA’s NVLink scale-up fabric using electrical or photonic interconnects, while NVLink-C2C provides high-bandwidth connectivity between compatible processors. NVHBM gives designers a route to customised high-bandwidth-memory integration while preserving more silicon area for compute.
MediaTek is adding its own custom-silicon, system-on-chip, connectivity, packaging, and manufacturing capabilities around that framework. Customers can therefore define the accelerator architecture and aspects of memory, connectivity, power, and package design without also having to create every surrounding interface from first principles.
The proposition is aimed particularly at hyperscalers and cloud companies developing application-specific XPUs. Custom accelerators can optimise training, inference, recommendation, or model-serving workloads more tightly than a general-purpose processor, but the economics weaken if every programme also requires a proprietary scale-up network, memory subsystem, and packaging architecture.
Advanced packaging is central to the problem because large AI processors are increasingly split across multiple dies. Reticle limits, yield, memory bandwidth, and thermal constraints make monolithic scaling progressively harder, while chiplets allow compute and I/O functions to be partitioned across different pieces of silicon. The package then becomes part of the system architecture rather than a passive carrier.
HBM compounds that integration challenge. Memory stacks sit close to the compute dies and demand wide, high-speed interfaces, controlled power delivery, and substantial heat removal. Any custom XPU therefore has to be co-designed with memory, package routing, thermal structures, and the rack-level fabric if it is to sustain useful performance outside a laboratory benchmark.
MediaTek and NVIDIA already collaborate on other compute platforms. Their work includes the GB10 Grace Blackwell Superchip used in DGX Spark, where a Grace CPU and NVIDIA GPU are connected through NVLink-C2C, as well as local-AI and automotive programmes. The expanded NVLink Fusion arrangement takes that relationship further into customer-specific data-centre silicon.
The $3.5 billion convertible-bond investment gives the collaboration a financial dimension that goes beyond a conventional IP agreement, but it does not guarantee production wins. No customer XPU based on the expanded arrangement was identified in the announcement, and custom-silicon programmes remain dependent on tape-out, packaging, qualification, manufacturing yield, software enablement, and eventual deployment.
There is also a strategic trade-off for customers. Using a prevalidated NVIDIA scale-up architecture can shorten development and lower integration risk, but it ties the resulting system more closely to NVIDIA’s interconnect and rack ecosystem. Some operators will consider that worthwhile if the alternative is recreating the surrounding infrastructure around every generation of accelerator; others may still favour proprietary fabrics where control of the full stack is a competitive objective.
MediaTek’s engineering opportunity therefore lies between those two positions. It can offer customers more differentiation than buying a standard accelerator while absorbing more of the integration burden than a completely bespoke programme. The expanded NVLink Fusion relationship strengthens that proposition, but the meaningful milestones will come when named customer designs move through tape-out, packaging, qualification, and volume deployment.
