IN Brief:
- UltraPin5000-EM expands digital pattern capacity and supports 5Gbit/s operation for increasingly complex compute devices.
- UltraPort-PCIe6 provides 64Gbit/s PAM4 PCIe Gen6 testing across 32 lanes per instrument.
- UltraVS64-HP delivers 1,280A per instrument and more than 15,000A at test-cell level.
Teradyne has added three instruments to its UltraFLEXplus automated test platform, extending digital pattern capacity, PCI Express Gen6 protocol testing, and high-current power delivery for increasingly complex AI and data-centre semiconductor devices.
The UltraPin5000-EM, UltraPort-PCIe6, and UltraVS64-HP address separate constraints inside the same automatic-test-equipment environment. Large accelerators increasingly combine extensive scan structures, high-speed serial interfaces, advanced packaging, and unusually high current demand, forcing test systems to exercise more functions without allowing pattern loading, signal integrity, or power delivery to dominate test time.
UltraPin5000-EM is Teradyne’s next-generation digital instrument for pattern-intensive compute devices. The company specifies up to 80 times more vector memory than competing market offerings and pattern loads up to ten times faster, while a Persistence Mode is designed to reduce reload delays during debug, characterisation, and production test. The instrument operates at data rates to 5Gbit/s and supports independent clock frequencies per pin.
Deeper vector memory reflects the size of modern structural-test workloads. Scan testing can involve very large pattern sets as manufacturers try to identify faults across billions of transistors, multiple chiplets, and dense package interconnects. Teradyne has also added scan-network acceleration that compiles per-core results in real time, allowing adaptive decisions to be made during test rather than waiting for an entire sequence to complete.
UltraPort-PCIe6 tackles the serial-I/O problem. Teradyne describes it as the industry’s first high-speed I/O protocol ATE solution for PCIe Gen6, delivering 64Gbit/s PAM4 operation across 32 lanes per instrument. Per-pin parametric measurement, integrated loopback, and a dedicated server-class compute backend with up to 2TB of memory are intended to keep protocol and scan workloads within the main tester rather than moving them to an external bench setup.
PCIe Gen6 presents a more difficult electrical environment than earlier generations because 64GT/s signalling uses PAM4. Four voltage levels carry two bits per symbol, increasing data throughput without doubling symbol rate but reducing voltage margin. Package transitions, sockets, probe interfaces, fixtures, loss, jitter, and reflections therefore become more difficult to control, particularly in production hardware that must remain repeatable across thousands of insertions.
Teradyne also supports mission-mode testing and high-speed I/O scan through UltraPort-PCIe6. The company is positioning that capability earlier in the manufacturing flow to improve confidence that a die is electrically sound before high-value HBM stacks and advanced packaging are added. The economics matter because a defect found after memory stacking or multi-die assembly can write off far more material than the original die alone.
The third instrument, UltraVS64-HP, addresses the power envelope. It delivers 1,280A per instrument, 5,120A with supplies ganged, and more than 15,000A at full test-cell level. A 16V range supports emerging integrated voltage-regulator architectures as well as lower-voltage, very-high-current devices, while integrated multi-point sensing is intended to hold the voltage at the device stable as current demand moves across large die and multi-die packages.
High-current semiconductor test is increasingly a thermal and protection problem as well as an electrical one. Fast load changes can produce local voltage droop and heating, while probe cards and sockets become expensive components exposed to fault energy. Teradyne has therefore added an Intelligent Power Interface with fast hardware-level fault response intended to guard against thermal runaway and damage to test hardware.
The instruments extend the same defect-detection logic Teradyne has been applying further downstream. Its Omnyx platform addresses AI-server board and subassembly testing, while UltraFLEXplus operates at wafer probe and final semiconductor test. In both cases, the objective is to find defects before more expensive packaging, memory, boards, and system hardware accumulate around them.
Manufacturers still have to decide which structural, functional, power, and interface tests justify their contribution to outgoing quality. More coverage is not automatically better if test time makes the device uneconomic. The value of the new instruments is that they expand headroom at three places where AI silicon is stretching conventional ATE: pattern depth, 64Gbit/s serial interfaces, and multi-kiloamp power delivery.
Those constraints are currently most visible in large accelerator devices, but they rarely remain confined to the top end of the market. As packaging density, interface speed, and current demand spread into a wider range of compute silicon, the production-test techniques being introduced for AI hardware are likely to become relevant to more conventional high-performance devices as well.