IN Brief:
- Synopsys has certified digital and analogue design flows for TSMC A14.
- Agentic AI work now extends into analogue migration and chiplet floorplan co-optimisation.
- N2P milestones include PCIe 7.0, HBM4, UCIe, and further multi-die power and optical-design support.
Synopsys and TSMC have extended their advanced node design collaboration with certified A14 flows, agentic AI automation, and additional support for multi-die systems using CoWoS and co-packaged optics. The September update adds specific certification, tape-out, power delivery, and interface IP milestones to an existing programme.
Synopsys says its digital and analogue implementation flows are now certified for TSMC A14, covering design implementation through sign-off. The companies are also working on device-routing enablement for advanced analogue place and route, where smaller geometries make manual layout increasingly expensive in engineering time.
The automation work extends into several design domains. Custom Compiler is being used for analogue migration, Fusion Compiler adds analysis assisted by large language models, and 3DIC Compiler introduces an agentic chiplet floorplan co-optimisation flow intended to automate part of the physical planning used in heterogeneous multi-die systems.
Chiplet floorplanning has to account for more than die placement. Interconnect length, routing density, power delivery, thermal behaviour, memory position, interposer constraints, and mechanical integration all influence whether a package can meet its performance and reliability targets. Improvements in one area can worsen another, leaving physical planning as a multivariable optimisation problem.
Automation also has to fit the verification regime already used by advanced node teams. A floorplan generated more quickly still has to pass timing, power, thermal, signal-integrity, and manufacturability checks, while design changes need enough traceability for failures to be reproduced and corrected before tape-out.
Power delivery is receiving additional attention through support for integrated voltage regulators on TSMC CoWoS. Synopsys says 3DIC Compiler can co-design and simulate IVR structures within the same environment used for package planning, bringing power integrity and thermal analysis closer to floorplan decisions instead of leaving them as late stage checks.
The companies are also continuing joint enablement around TSMC-COUPE for co-packaged optics. The flow combines photonic and electronic design with 3DIC implementation and multiphysics analysis, reflecting the need to verify optical structures, electrical drivers, heat, signal integrity, and package behaviour as a connected system.
Interface and foundation IP provide some of the clearest implementation milestones in the update. Synopsys reports N2P activity covering PCIe 7.0, HBM4, LPDDR6 and earlier LPDDR generations, 224G Ethernet PHY, UCIe, one-time-programmable memory, and process, voltage, and temperature monitoring IP.
It has also demonstrated UCIe-A 32G and 40G silicon on an N3P test chip integrated with a CoWoS-S interposer and reports 64G UCIe tape-outs on both 2nm and 3nm nodes. Such interface work is central to chiplet architectures because reusable die-to-die links reduce the need for each multi-die programme to create a separate proprietary interconnect.
The latest announcement follows earlier Synopsys and TSMC design enablement work covering AI-assisted EDA, A14, CoWoS, and co-packaged optics. The new material is therefore concentrated on certification progress, agentic workflow extensions, IVR co-design, and fresh interface IP milestones rather than a new partnership.
That narrower scope is useful when assessing the AI element. Agentic design tools are being introduced into established implementation environments with existing sign-off requirements, so their value will depend on whether they reduce repetitive migration, analysis, and floorplanning work without weakening traceability or making late stage failures more difficult to diagnose.
Advanced node and multi-die projects already involve more interactions between process technology, package architecture, memory, power delivery, thermal limits, and reusable IP than one discipline can handle independently. Consolidating those constraints inside shared design flows can shorten iteration, but certification and successful IP tape-out remain steps towards customer silicon rather than proof that every design will converge more quickly.
The September milestones move more of that work into a common methodology spanning die, package, power, optics, and reusable interfaces. Customer tape-outs will provide the more meaningful test of whether the new automation and co-design functions reduce design cycles while maintaining the power, performance, thermal, and reliability targets expected from advanced AI and HPC systems.
