Renesas shrinks programmable GreenPAK to 1.155mm

Renesas shrinks programmable GreenPAK to 1.155mm

Renesas adds multi-time programmability to its smallest GreenPAK device yet. The SLG46801 combines mixed-signal logic, analogue comparators, counters, and I²C configuration in WLCSP and STQFN packages.


IN Brief:

  • The nine-ball WLCSP measures 1.155mm × 1.155mm, with a 12-lead STQFN version providing additional I/O.
  • Multi-time programmable memory allows configuration changes after the device has been installed in a system.
  • Operation and programming are supported across a 1.71V to 5.5V supply range.

Renesas Electronics has expanded its GreenPAK configurable mixed-signal range with the SLG46801, combining multi-time programmable logic and analogue functions in a nine-ball WLCSP measuring 1.155mm × 1.155mm.

The company has started sampling the device as a compact option for implementing small collections of glue logic, comparators, timers, and supervisory functions without spreading the design across several discrete components. A 12-lead STQFN package measuring 1.6mm × 1.6mm is also available where additional I/O is required.

The most substantial addition is multi-time programmable memory combined with an I²C-compatible interface. Renesas says the non-volatile configuration can be changed after the component has been installed in the end system, allowing logic updates or bug fixes without replacing the IC.

Both normal operation and programme or erase functions are supported from a 1.71V to 5.5V supply. The wide range allows the SLG46801 to sit alongside several common logic and mixed-signal voltage domains without introducing a separate programming supply.

Configurable resources include two high-speed analogue comparators, three combination-function macrocells that can operate as three-bit lookup tables or flip-flop and latch functions, and three further multifunction macrocells combining selectable storage functions with lookup tables and eight-bit delay counters.

The device also incorporates programmable delay functions, three eight-bit delay counters, 10kHz and 25MHz oscillators, and power-on reset with an optional cyclic redundancy check. Read-back protection is provided for the stored configuration.

GPIO capability varies with package choice. Renesas provides one tolerant GPIO on the WLCSP version and two on the STQFN device, allowing those pins to be driven above the IC supply voltage within their specified limits. The STQFN option increases the available GPIO count while retaining the same core programmable architecture.

GreenPAK devices occupy the space between fixed-function logic and analogue components and larger programmable devices. The aim is not to replace a microcontroller or FPGA, but to absorb relatively small board-level functions that might otherwise require several ICs and passive components.

A typical design may need reset sequencing, timing, threshold detection, level handling, state logic, or simple signal conditioning around the main processor. None of those functions necessarily warrants another programmable processor, but implementing each separately increases board area, assembly count, and the number of components that have to be sourced and qualified.

The 1.155mm square WLCSP extends that approach into particularly space-constrained equipment. Renesas identifies wearables and portable systems among the applications, while the wider product page also lists networking, computing, storage, smart-home, IoT, and consumer-electronics designs.

Repeated programming changes the development process as well as the component count. A timing or logic change discovered during prototype work can be loaded through the I²C interface rather than requiring a fresh one-time-programmed device, provided the required behaviour remains within the SLG46801’s available resources.

The architecture still has clear limits. Applications requiring substantial firmware, communications stacks, memory, or complex processing remain better suited to a microcontroller or larger programmable device. The SLG46801 is designed for a narrower set of hardware functions where deterministic logic and mixed-signal behaviour can be configured without adding another software-controlled subsystem.

Keeping simple supervisory or timing functions in hardware can also isolate them from processor boot time, software scheduling, and application loading. That can be useful where a small control function has to remain predictable before the main processor is fully operational.

Renesas has begun sampling the SLG46801 and says mass production of the WLCSP version is scheduled for November 2026. The combination of repeated in-system configuration and a 1.155mm package gives designers another option where board space is tight but the required logic is still expected to change during development or product life.


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