IN Brief:
- Sapphire RV64 uses a seven-stage RISC-V64IM pipeline with configurable ISA extensions, caches and on-chip memory.
- An optional SV39 MMU supports Linux, while the memory controller handles DDR3, HyperRAM and LPDDR4x at up to 3,200Mbps.
- RV64 is available across Titanium, Topaz and Trion T20-and-above FPGAs through the existing Efinity development environment.
Efinix has expanded its Sapphire processor family with the RV64 SoC, adding a configurable 64-bit RISC-V core for FPGA designs that need larger memory spaces, deeper caches and more capable embedded Linux support.
Sapphire RV64 uses a seven-stage pipeline implementing the RISC-V64IM instruction set, with optional A, F, D and C extensions alongside Zba, Zbb, Zbs and Zicbom. The architecture extends Efinix’s existing 32-bit Sapphire approach rather than introducing a separate processor development environment.
On-chip RAM can be configured from 4KB to 512KB. Multi-way L1 instruction and data caches are supported alongside an optional L2 cache, branch predictor and hardware or software prefetchers, allowing processor resources to be adjusted against the available FPGA fabric.
An optional SV39 memory management unit provides the virtual memory support required for more capable Linux environments. The external memory controller supports DDR3, HyperRAM and LPDDR4x at data rates up to 3,200Mbps, giving the processor access to multi-gigabyte memory configurations beyond the practical address range of a 32-bit embedded core.
The move to 64-bit processing is therefore less about changing the instruction set philosophy than removing resource limits around larger applications. Edge AI workloads, image buffers and richer Linux software stacks can place greater demands on addressable memory and cache capacity than the control-oriented applications typically handled by a smaller soft processor.
Sapphire RV64 is available across all Efinix Titanium and Topaz FPGAs and on Trion devices from T20 upwards. That allows the same processor architecture to scale across several FPGA families, although the exact CPU configuration, cache resources, external memory and hardware accelerators will still depend on the target device.
Configuration takes place through Efinity IP Manager and the Efinity integrated development environment. Software development uses the Eclipse-based Efinity RISC-V Embedded Software IDE, covering software development, debugging and board support package integration within the company’s existing toolchain.
Debug capability has also been expanded for the 64-bit core, including FPGA co-debug functions intended to give developers visibility into software and surrounding programmable logic. That interaction is important in a soft SoC because the processor rarely operates as an isolated block.
The surrounding FPGA can implement custom interfaces, signal processing or workload-specific accelerators while the RISC-V core handles operating system functions and higher level software. Efinix retains the custom instruction mechanism used in its 32-bit Sapphire architecture, allowing software operations to invoke functions implemented directly in programmable logic.
That creates another route to performance beyond raising CPU throughput. A computationally expensive operation can be moved into dedicated FPGA logic while remaining exposed through the processor’s software environment, allowing the balance between software and hardware to change as the application is developed.
Edge AI is one application for that arrangement. The processor can handle networking, configuration, model orchestration and system management while programmable logic carries out selected preprocessing, data movement or inference functions. The useful split depends on the workload rather than the presence of a 64-bit core alone.
The architecture still carries conventional FPGA trade-offs. Larger caches, memories and processor options consume resources that could otherwise be allocated to custom logic, while external memory bandwidth has to serve both software and hardware accelerators. A maximum-feature processor configuration is therefore not automatically the best implementation for every device.
Efinix has designed RV64 as a migration route for users of its existing 32-bit Sapphire SoCs. Keeping the configurable architecture, custom instruction model and development tools consistent reduces the amount of system redesign required when a product needs to move beyond 32-bit memory and software limits.
The company has not attached a single clock rate or benchmark result to the announcement. Performance will depend on the FPGA family, processor configuration, memory architecture and timing achieved in the complete design, making resource utilisation and timing closure as relevant as the CPU specification itself.
Sapphire RV64 is available now for supported Titanium, Topaz and Trion devices. The new core removes a ceiling within the existing Sapphire architecture, allowing larger memory footprints and more capable Linux applications while keeping software processing closely coupled to programmable hardware acceleration.
