IN Brief:
- Structera X 3406 supports up to 18 DDR4 RDIMM slots and 9TB, while the DDR5-based 3506 supports 12 slots and 6TB.
- The controllers offer four-host CXL connectivity, inline LZ4 compression and integrated memory reliability and security features.
- Marvell expects to begin sampling both CXL 3.2 controllers in the first quarter of 2027.
Marvell Technology has introduced two six-channel CXL 3.2 memory expansion controllers for AI computing systems, with a DDR4 model and a separate DDR5 design. The Structera X 3406 and 3506 connect expanded memory through a PCIe 6.0 host interface, offering a way to increase available DRAM capacity beyond a server processor’s directly attached memory channels. Customer sampling is planned for the first quarter of 2027, while the company’s earlier four-channel controllers are already shipping.
Marvell specifies 18 DDR4 RDIMM slots and up to 9TB of supported capacity for the 3406, compared with 12 DDR5 RDIMM slots and up to 6TB for the 3506. Six channels represent an increase of 50% over its four-channel Structera X 2404 and 2504 devices. The quoted capacities depend on the type and density of installed memory modules and on the surrounding expansion-board design; the controllers themselves do not contain that amount of DRAM.
Compute Express Link, or CXL, is a coherent interconnect that can expose memory located outside the processor’s conventional DIMM channels. An expansion card or memory appliance can add addressable capacity without filling more sockets on the host motherboard. Data must nevertheless cross the CXL interface before reaching the processor, so bandwidth, access latency and application placement have to be evaluated separately from directly attached DRAM. A larger capacity pool will not automatically improve the performance of every workload.
The controllers support connections to as many as four hosts, allowing suitably configured systems to share access to expansion memory rather than permanently reserving all of it for one server. Marvell quotes up to 256GB/s of host-interface bandwidth for PCIe 6.0 x16. That is a nominal aggregate figure for the bidirectional interface, rather than a guaranteed one-way application transfer rate. Effective throughput will depend on link overheads, topology, memory access patterns and the software managing allocation across hosts.
Inline LZ4 compression is another feature of the new devices. Marvell specifies combined compression and decompression throughput of up to 250GB/s, which it says is five times the throughput of the preceding generation. The company also claims that suitable workloads can obtain two to three times the effective memory capacity. Compression increases the quantity of logical data that can fit into a physical allocation, but already compressed or incompressible data cannot be expected to achieve the same gain.
AI inference is a stated application because transformer-based systems retain key-value cache data that grows as context is processed. Recommendation systems can similarly maintain large embedding tables. Keeping more such working data in addressable memory may reduce pressure to move data between storage tiers, provided the application and runtime can place it appropriately. An expansion device does not remove the cost of moving data through the link, and a latency-sensitive portion of a model may still be better retained in local memory.
For selected large-language-model workloads, Marvell reports 40–50% faster time to first token at an equivalent context length, or up to twice the supported context window at equivalent latency, against its first-generation products. The company also cites up to twice the number of queries per second in selected recommendation workloads. These are manufacturer comparisons, not general benchmark guarantees; system configuration, model characteristics and the placement of compressed data determine the result in an individual installation.
Memory reliability and security involve several different mechanisms. The announced features include StructGuard error correction, CXL integrity and data encryption, AES-256 memory encryption, Caliptra 2.0 and post-quantum cryptographic functions. Error correction deals with certain memory faults, whereas encryption protects information and firmware-rooted mechanisms can support platform trust. The availability of these capabilities in a controller does not, by itself, demonstrate certification or full end-to-end security of a deployed server.
Firmware discovery, operating system support and pooling policies must establish which hosts may access each region of expanded memory and how access is recovered after a server fault. The four-host configuration will need validation against those allocation and recovery behaviours in the finished platform.
Marvell is demonstrating the forthcoming controllers at the Open Compute Project Global Summit in San Jose. Customer samples are targeted for the first quarter of 2027. Subsequent deployments will depend on host-processor and memory-module qualification, board integration, system software and measured results under representative workloads.
