IN Brief:
- Preferred Networks and Tenstorrent have secured selection for a five-year NEDO research programme developing AI processors incorporating photonics-electronics integration.
- The work covers system integration, AI chiplets with three-dimensional memory stacking and open-architecture CPU chiplets supporting confidential computing.
- Japanese research organisations will investigate scientific and physical AI applications; prototype specifications and commercial performance remain unannounced.
Preferred Networks and Tenstorrent have been selected for a five-year Japanese research programme developing artificial intelligence processors that incorporate photonics-electronics integration, advanced semiconductor packaging and specialised chiplet architectures. The project, supported by the New Energy and Industrial Technology Development Organization, or NEDO, will investigate ways to combine high-bandwidth memory, processor components and optical communication within computing systems designed for AI training and inference.
The companies confirmed their selection on 20 October under NEDO’s programme for strengthening the infrastructure required by post-5G information and communications systems. Their proposal covers system-level integration, three-dimensional memory stacking and CPU chiplets supporting confidential computing, with additional research involving Japanese universities and scientific institutions.
Preferred Networks and Tenstorrent will jointly develop technologies for integrating AI processors through photonics-electronics convergence and advanced packaging. Preferred Networks will concentrate on AI chiplets incorporating very high memory bandwidth through stacked memory technology, while Tenstorrent will develop open-architecture CPU chiplets designed to support confidential computing.
The research is intended to address the increasing demand placed on data movement within advanced computing hardware. AI models require repeated calculations involving large arrays of numerical values, while processors must obtain data from memory and exchange information with other computing components. Those operations consume electrical power and can constrain performance when communication bandwidth does not keep pace with arithmetic capability.
Conventional electronic connections remain essential to semiconductor systems, but high data rates introduce challenges involving signal integrity, conductor geometry and power consumption. The electrical characteristics of an interconnect become increasingly important as transmission speeds rise and the distance between components changes.
Photonics-electronics integration provides an alternative for selected connections by transferring information through optical signals. Appropriate photonic interfaces can support communication between semiconductor components, although electronic-to-optical conversion and the reverse process introduce additional devices and energy requirements.
The advantages must therefore be evaluated across the complete connection rather than from optical transmission alone. Optical sources, modulators, receivers and associated electronic circuits all contribute to power consumption, while the package must provide suitable optical alignment and maintain acceptable thermal behaviour.
Chiplet architectures create opportunities to combine different functions within one advanced package. Instead of incorporating every function into a single large die, designers can use separately fabricated semiconductor components for processing, memory interfaces and supporting functions. The resulting system depends on sufficiently fast and reliable connections between those components.
Preferred Networks will investigate AI chiplets using three-dimensional memory stacking based on advanced semiconductor process technologies. Stacking memory structures can increase the density of connections between memory and computing hardware, potentially providing greater bandwidth within the space available for a package.
That arrangement also introduces manufacturing and thermal constraints. Vertically integrated devices require reliable connections through the assembly, while the resulting concentration of active circuitry can make heat removal more demanding. Yield is affected by the quality of the individual dies and the processes used to combine them.
Memory bandwidth is only one element of overall computing performance. A processor must be able to use the data delivered by its memory system, and software must organise the workload so that arithmetic resources remain appropriately supplied. Higher theoretical bandwidth does not automatically produce an equivalent improvement in application throughput.
Tenstorrent’s contribution involves CPU chiplets based on an open architecture and designed to support confidential computing. The company’s wider processor development includes RISC-V technology, although the precise instruction set, microarchitecture and security implementation of the new chiplets have not been disclosed in the project announcement.
Confidential computing aims to protect selected information and processing operations while a system is running. Depending on the architecture, hardware-enforced boundaries can restrict access to protected data by other software components or parts of the wider computing environment.
Providing those protections requires appropriate processor features, memory controls and supporting software. Cryptographic functions, execution isolation and the handling of transitions between protected and ordinary operations must work together if the resulting system is to provide meaningful security guarantees.
Tenstorrent Japan will contribute CPU chiplet design and software for demonstrating confidential computing. The programme does not establish that a completed secure processor has already passed independent evaluation, or that the intended security features have been qualified for any particular application.
Advanced packaging will connect these research activities. Optical and electronic components can use different materials and fabrication processes, while the completed package must provide precise optical interfaces, electrical connections and heat transfer paths.
Maintaining optical alignment during manufacture and operation is an important consideration because small positional differences can affect coupling losses. The relationship between the optical components and the electronic processing hardware must also remain stable under relevant mechanical and temperature conditions.
The five-year programme includes research on applications for scientific AI and physical AI. The University of Tokyo, Kobe University, Toyo University, the Japan Agency for Marine-Earth Science and Technology, and the Japan Atomic Energy Agency will contribute as subcontracting research partners.
Scientific AI workloads may involve numerical modelling and simulation, while physical AI applications can include perception and decision-making systems that interact with equipment or the surrounding environment. Their requirements differ in numerical precision, memory use and the time available for individual calculations.
Evaluating the proposed processor architecture against several workload categories can help determine which combinations of processing, memory and communication provide practical advantages. However, no specific application benchmark or completed hardware result has been disclosed for the newly selected project.
The research is distinct from the separate NEDO optical chiplet manufacturing programme involving NTT Innovative Devices and its partners. That project targets manufacturing methods and a pilot production line, whereas Preferred Networks and Tenstorrent are concentrating on processor architecture, chiplets and system-level integration.
The companies intend to investigate commercial applications after the research programme, including AI agents and other computing workloads. They have not announced a fabricated xPU, a commercial release date or measured improvements in power consumption and processing throughput. Those characteristics will depend on prototype development and testing as the programme progresses.



