Rambus adopts ChipAgents for semiconductor design

Rambus is adopting the ChipAgents agentic artificial intelligence platform across its chip and silicon intellectual property engineering operations, extending the use of AI-assisted tools into design, verification, and integration workflows.

The agreement, announced on 22 October, also makes Rambus a strategic investor in ChipAgents. The companies plan to combine Rambus semiconductor expertise with ChipAgents software to assist customer design work across preferred electronic design automation environments. Neither the investment amount nor a timetable for completing the companywide deployment has been disclosed.

Rambus develops memory interface technologies, chips, and silicon IP used in data centre and AI computing infrastructure. These functions have to operate with processors, memories, and other circuitry designed by different suppliers, making predictable signalling and correct integration important to the behaviour of the finished semiconductor.

ChipAgents develops software agents intended to work with design specifications, source code, register-transfer-level descriptions, and verification results. Its platform is presented as a way to coordinate engineering tasks through established design tools rather than requiring an organisation to replace every application in its existing toolchain.

At register-transfer level, digital hardware is described through registers, logical operations, and the transfer of information between them. An RTL description can be simulated before manufacture, allowing engineers to evaluate whether a circuit produces the intended outputs for defined inputs and operating conditions.

Functional simulations cannot by themselves establish that a circuit has been tested adequately. Complex IP blocks contain operating states and interactions that may be difficult to exercise, particularly when events occur concurrently or when communication interfaces encounter faults. Verification teams therefore develop targeted tests, assertions, and analyses to examine more than routine operation.

An AI agent could assist by examining a requirement, preparing a candidate implementation, invoking a simulator, and analysing reported errors. The resulting proposal still needs to be checked against the original specification, since a generated test can repeat an incorrect assumption found in generated design code.

A reusable silicon IP block that has passed verification in one design must still be matched to the clock structure, reset sequence, address map, and communication interfaces of the next chip in which it is used. Engineers check that signal timing and operating sequences remain compatible, including during startup and fault recovery.

Memory interface IP can be particularly sensitive to timing assumptions. Signals must be exchanged within defined intervals, and an apparently minor change to the surrounding logic or physical implementation can affect whether the complete interface operates correctly at its intended speed.

The partnership is intended to apply ChipAgents capabilities to those engineering tasks while allowing customers to retain their chosen design environments. Tool-agnostic operation is important because semiconductor organisations commonly combine software from multiple suppliers for simulation, synthesis, implementation, and checking.

Maintaining that flexibility requires the agent platform to interpret outputs from different tools and keep track of their settings. A timing report, for example, only has meaning in relation to the timing constraints and design version used to generate it. Recommendations based on an outdated configuration can be misleading.

Rambus and ChipAgents also intend to improve quality of results, the term used for outcomes such as timing, power consumption, and silicon area in a design process. Those objectives can compete: adding circuitry to improve timing may increase area or power demand, while reducing area may introduce new routing constraints.

Consequently, an automated optimisation has to be assessed against the complete set of requirements rather than one attractive result. A design that passes functional simulation but fails timing analysis or physical design checks cannot be considered ready for implementation merely because an AI system generated it quickly.

Engineers must trace each proposed change to its requirements, validate the resulting implementation, and preserve the evidence supporting its acceptance. They must also review tool-generated modifications against the complete system, particularly where third-party intellectual property is involved.

Because AI-assisted verification draws on specifications, RTL source files, test results, and IP integration details, the workflow may process confidential material owned by several organisations. Access to that information must follow the permissions and confidentiality terms of the engineering programme as data passes between the agent platform and connected design tools.

ChipAgents describes broader capabilities for generating RTL, verification assets, and failure analysis, but the Rambus announcement does not identify a completed production chip developed using the new arrangement. It also provides no independently measured reduction in project duration, verification effort, or manufacturing cost attributable to this partnership.

Rambus says it will deploy the platform within its own chip and silicon IP workflows while the partners collaborate on customer-facing integration capabilities. Results from individual engineering projects will be needed to establish whether the proposed workflow delivers measurable improvements without compromising design verification or implementation requirements.