IN Brief:
- Variscite and SecEdge have integrated SEC-TPM firmware support across i.MX 6, 7, 8 and 9 module families.
- The implementation runs within OP-TEE using TrustZone isolation, with EdgeLock Secure Enclave support on suitable i.MX 93 and 95 devices.
- EU Cyber Resilience Act reporting obligations began on 11 September 2026; the main requirements apply from 11 December 2027.
Variscite and SecEdge have integrated firmware-based Trusted Platform Module 2.0 functions into Variscite’s NXP i.MX system-on-module range, giving embedded developers a way to implement standard security services without adding a separate TPM integrated circuit.
SEC-TPM firmware is documented and available for Variscite modules using i.MX 6, i.MX 7, i.MX 8 and i.MX 9 processors. The companies intend it for existing designs as well as new products, provided the selected hardware and secure firmware configuration support the implementation.
The Trusted Computing Group’s TPM 2.0 specification defines services for cryptographic operations, protecting sensitive keys and establishing device identity. Applications can use these services through defined software interfaces rather than handling every secret within ordinary application memory.
A conventional TPM commonly takes the form of a separate security chip connected to the main processor. Firmware TPM provides related functions through software executing in a protected part of an existing processor, reducing component count and avoiding the board changes needed to accommodate another device.
SEC-TPM runs in the secure world of OP-TEE, a trusted execution environment that uses Arm TrustZone isolation on compatible processors. Access controls separate selected secure operations and memory resources from applications running in the normal execution environment.
TrustZone supplies mechanisms for separation, but system security depends on their configuration and on the integrity of the trusted firmware. A flaw in secure-world software or in how interfaces are exposed can undermine the protection even if the processor includes the required architectural features.
Suitable i.MX 93 and i.MX 95 modules offer an additional hardware root of trust through NXP’s EdgeLock Secure Enclave. SEC-TPM can make use of that facility, but earlier i.MX families do not all have the same security architecture, and their implementations should not be described as identical.
A hardware root of trust supplies a protected basis for selected cryptographic functions. The TPM implementation makes defined security services available to the wider system, while provisioning, secure boot and software updates must be implemented and assessed separately.
Device identity is one application. Protected credentials can allow a connected product to authenticate itself when communicating with management software or other equipment. Key protection is valuable where devices operate in industrial locations without constant physical supervision.
Authentication depends on how keys are generated, introduced into devices and managed throughout service. A protected key store does not address the risks created by weak provisioning procedures, compromised account permissions or improperly authenticated firmware updates.
Firmware TPM can also support measured boot, recording information about components loaded during startup. Such measurements can be used to assess the expected software state, but measuring a component is different from preventing unauthorised software from executing.
Secure boot requires an enforcement mechanism that checks whether firmware is authorised. TPM functions may contribute to the broader design without replacing the boot architecture, code-signing policies or recovery arrangements established for the product.
The implementation is intended to support devices already in service where the necessary update mechanism exists. Installing firmware security features without a hardware redesign could be useful for established embedded products, but a field update still requires testing against the existing boot process, operating system and application software.
Integration work may include trusted firmware configuration, board support package changes and adaptation of applications to use TPM interfaces. Moving credentials from existing storage to protected functions also calls for an appropriate migration and recovery strategy.
The European Union’s Cyber Resilience Act is increasing the need for documented security controls in embedded products. The Act’s reporting provisions began applying on 11 September 2026, requiring manufacturers of products within scope to report actively exploited vulnerabilities and qualifying severe security incidents.
The reporting process includes an early warning within 24 hours of awareness and a more complete notification within 72 hours. Main product cybersecurity requirements are scheduled to apply from 11 December 2027, subject to the legislation’s scope and transitional provisions.
Products placed on the market before that main application date are subject to distinct transitional treatment. Reporting obligations already apply to products within scope, while the applicability of the main product requirements to previously marketed products depends in part on whether they undergo substantial modification after the relevant date.
A TPM can support cryptographic protection and device authentication, but does not fulfil obligations concerning vulnerability handling, risk assessment, incident reporting or software maintenance by itself. Compliance must be assessed for the complete product and the manufacturer’s processes.
Variscite provides maintained board support packages and product longevity programmes of seven to 15 years for selected modules. Individual customers must still establish which support arrangements cover their chosen hardware, software versions and deployment periods.
The companies have not provided a comparative benchmark of SEC-TPM against discrete TPM devices across every supported processor. Developers can now evaluate the firmware on available i.MX modules, with the resulting security properties dependent on processor capabilities and implementation of the complete device.
