Altera demonstrates 100G FPGA ultrasound streaming

Altera demonstrates 100G FPGA ultrasound streaming

Altera demonstrates FPGA sensor streaming within an ultrasound imaging system. Its GTC Berlin installation combines Terasic hardware, Texas Instruments ultrasound electronics and NVIDIA Holoscan, providing a high-bandwidth acquisition path towards GPU processing.


IN Brief:

  • Altera demonstrated its Stratix 10 TX-based 100G Holoscan Sensor Bridge with an ultrasound imaging arrangement developed by Yuan at GTC Berlin.
  • The demonstration combines a Texas Instruments ultrasound evaluation module with Yuan's NEAR 7TX T7000-based system and Terasic sensor aggregation hardware.
  • NVIDIA Hololink and GPUDirect RDMA support transfer towards GPU memory, but no measured clinical performance or complete acquisition-to-display latency was disclosed.

Altera has demonstrated its 100G FPGA-based Holoscan Sensor Bridge in an ultrasound imaging system at NVIDIA GTC Berlin, connecting sensor acquisition hardware with accelerated image processing. Developed by Yuan, the demonstration combines a Terasic FPGA sensor aggregation platform, a Texas Instruments ultrasound evaluation module and a Yuan NEAR 7TX T7000-based system to establish a high-bandwidth path between acquisition electronics and GPU computing.

The demonstration, announced on 21 October, applies Altera’s existing Holoscan Sensor Bridge technology to a defined medical imaging workflow. It does not represent the first introduction of the FPGA reference platform. The current development is the integration of ultrasound acquisition, sensor transport and processing into an operating demonstration intended to show how imaging data can be delivered to an accelerator with reduced dependence on conventional host CPU capture.

The system uses Altera’s Stratix 10 TX FPGA within the Terasic Sensor Processing Kit, providing a programmable interface capable of transporting sensor data over 100Gb Ethernet. NVIDIA Hololink and GPUDirect remote direct memory access support the movement of information towards GPU memory, where an application built using NVIDIA Holoscan can process the incoming data.

Ultrasound imaging begins with the transmission of acoustic pulses into the body and the detection of returning echoes. Transducer elements convert those echoes into electrical signals, which are conditioned and digitised before processing. The amount of data generated depends on the number of acquisition channels, sampling frequency, resolution and the selected imaging method.

Constructing an image from those signals requires operations involving timing, beamforming and other numerical processing. When the data is acquired by one device and processed by another, the transfer between them becomes part of the imaging system’s overall latency and throughput requirements. The acquisition and transport stages must also preserve the information needed to interpret measurements from different sensor channels correctly.

Conventional acquisition arrangements may transfer sensor information through the host processor before it reaches a graphics accelerator. That path can introduce memory copies, software interrupts and variability associated with operating-system scheduling. These costs become more demanding when an application must process several incoming data streams within consistent timing constraints.

Altera’s FPGA architecture performs selected capture and transport functions directly in programmable logic. Incoming information can be formatted, timestamped and assembled into network packets through hardware pipelines operating in parallel. The resulting data can then be transmitted across a standard Ethernet interface towards the receiving processing platform.

FPGA-based aggregation provides a degree of flexibility because the acquisition interface is not restricted to a single fixed-function sensor protocol. Depending on the device and supporting intellectual property, programmable logic can accommodate different camera, converter and industrial interfaces. The surrounding PCB must still provide compatible electrical connections and signal conditioning, so reconfiguration does not automatically eliminate all hardware changes.

At the receiving end, NVIDIA’s Holoscan Sensor Bridge approach is intended to reduce software involvement in the principal data path. GPUDirect RDMA allows suitably configured network hardware to transfer data towards GPU memory without requiring the same sequence of host-mediated copies used in conventional capture arrangements.

The resulting architecture can reduce some sources of transfer overhead and timing variation, although its actual performance depends on the network interface, packet handling, buffering and application configuration. A connection rated at 100Gb Ethernet does not establish that the ultrasound system produces 100Gbit/s of image data or that the end-to-end application sustains that throughput.

The bandwidth available to useful sensor payloads is also affected by Ethernet framing and transport overhead. The processing pipeline must receive data at a rate it can handle without unacceptable buffering delays or losses. In an imaging application, acquiring information quickly provides limited benefit if processing, reconstruction or display introduces excessive additional latency.

Altera offers related reference implementations using Agilex 5 FPGAs at 10Gb and 25Gb Ethernet speeds. The Stratix 10 platform provides an alternative at the higher bandwidth end of the portfolio. These options allow developers to select an arrangement according to the number and characteristics of their sensors, available processing resources and communication requirements.

The demonstration is relevant to several acquisition technologies, but they do not all have identical requirements. Ultrasound, multispectral cameras, conventional image sensors and computed tomography systems generate different data structures and may require specialised processing before useful information becomes available. Supporting more than one sensor type therefore involves appropriate acquisition interfaces and application software, not simply replacing one camera or transducer with another.

Medical equipment development introduces additional requirements beyond data transport. Acquisition accuracy, signal integrity, consistent timing and appropriate error handling must be established for the intended application. Where software contributes to diagnosis or clinical decision-making, its performance and applicable regulatory requirements must be evaluated separately from the underlying communication hardware.

Neither Altera nor Yuan has disclosed a complete measurement of acquisition-to-display latency for the GTC Berlin arrangement. The material also does not establish a quantified improvement in diagnostic accuracy, medical device clearance or commercial deployment of the demonstrated ultrasound system. The operating installation confirms that the named hardware and processing technologies can be integrated, rather than proving that the complete arrangement satisfies the requirements of a marketed clinical device.

Altera makes its Stratix 10 Sensor Bridge example design available on request under a licensing arrangement, while related Agilex 5 reference designs provide other development paths. Further engineering assessment will depend on measured latency, sustained throughput, acquisition fidelity and the behaviour of the complete system under representative operating conditions.


Stories for you


  • Japanese consortium advances optical chiplet manufacturing

    Japanese consortium advances optical chiplet manufacturing

    Four Japanese companies will develop manufacturing processes for optical chiplets. The NEDO-backed programme combines photonic device production, silicon photonics and advanced packaging, targeting a pilot line and substantially greater manufacturing productivity.


  • TAIYO YUDEN integrates component data into OrCAD X

    TAIYO YUDEN integrates component data into OrCAD X

    TAIYO YUDEN adds extensive component data within Cadence OrCAD X. The integration makes characteristics for approximately 10,000 capacitors and inductors available within an established PCB design environment, supporting component selection and circuit simulation.