IN Brief:
- The EPIC facility covers 600,000 square feet, including almost four acres of advanced cleanroom space.
- Founding chipmaker partners include TSMC, Intel, Samsung Electronics, SK hynix and Micron.
- Applied Materials says capital expenditure will increase towards approximately $5bn as customer projects begin.
Applied Materials has unveiled its Equipment and Process Innovation and Commercialization centre in Sunnyvale, California, marking the physical completion of a 600,000-square-foot semiconductor research facility built for joint process development. Known as EPIC, the centre contains nearly four acres of advanced cleanroom space and brings chip manufacturers, equipment suppliers and academic researchers into a common development environment. Applied describes an investment programme that will grow to approximately $5 billion as customer projects begin, rather than $5 billion already spent on the completed building.
The facility follows a succession of agreements with semiconductor companies and universities announced throughout 2026, including recent partnerships covering advanced packaging, memory development and materials research. Those individual collaborations have already been the subject of separate announcements. The new milestone is the unveiling of the constructed centre and the consolidation of the partner programmes within its planned research infrastructure.
Applied says the building required more than six million construction hours and contains purpose-built cleanrooms for advanced process and equipment research. Cleanroom conditions control particles and other contaminants that could interfere with the extremely small structures formed on semiconductor wafers. Physical proximity between experimental tools is also important because a change in one manufacturing step can alter how a material behaves during later deposition, patterning or etching operations.
Semiconductor process development has traditionally involved transfers between materials researchers, equipment builders and device manufacturers, with separate engineering teams refining each stage before the next group tests it. Such sequential handovers can create repeated qualification and redesign cycles when individual processes do not behave as expected in an integrated flow. Applied intends to carry out more of this work in parallel, allowing tool settings, materials and device structures to be investigated together before a customer commits to a production recipe.
The centre opens with founding chipmaker partners TSMC, Intel, Samsung Electronics, SK hynix and Micron, alongside equipment and technology collaborators including Broadcom, Advantest, SCREEN, Kioxia and Besi. Academic participants include Stanford University, the University of California at Berkeley, UCLA, Arizona State University and Rensselaer Polytechnic Institute. The breadth of the group does not mean intellectual property or individual customers’ manufacturing data will be shared indiscriminately: the company describes secure collaboration arrangements and programmes tied to specific development requirements.
Joint research is intended to address transistor structures, wiring materials, memory devices and advanced packaging, all of which face increasingly demanding manufacturing tolerances. As structures become smaller or more three-dimensional, a new material can affect interface resistance, film uniformity or downstream process temperatures. Evaluating those interactions together may identify problems earlier than testing each material or tool independently, but commercial value will ultimately depend on reproducible process windows and acceptable yields in production fabs.
The involvement of memory manufacturers adds another set of process constraints. High-bandwidth memory and other densely stacked devices require precise manufacturing of multiple layers and reliable connections between them, while the package must manage heat and deliver adequate electrical performance. Research undertaken in a shared cleanroom can contribute to solutions, although no newly qualified production node, yield figure or customer chip launch was disclosed as a direct outcome of the unveiling.
Applied’s stated aim is to shorten the path from materials research to high-volume manufacturing by involving customers earlier in equipment and process development. That does not remove the qualification work required inside each manufacturer’s own fab, where process integration, maintenance, reliability and supply requirements differ. The economic outcome will depend on whether discoveries made in EPIC can be transferred efficiently into production recipes without introducing new variability or equipment bottlenecks.
The completed Sunnyvale building gives the named research partners a common facility in which to begin their programmes, while capital investment is expected to reach approximately $5 billion as activity expands. Whether jointly developed processes enter commercial fabs more quickly will depend on qualification results and adoption by customers; neither has yet been demonstrated by the opening of the centre.
