IN Brief:
- Arm is expanding its use of the Cycuity Radix hardware-security platform.
- The tools analyse attack surfaces and trace potential weaknesses before processor designs reach silicon.
- Reusable security properties can reduce duplicated verification work across successive CPU programmes.
Arm is expanding its use of the Cycuity Radix hardware-security assurance platform across additional next-generation CPU programmes, moving more vulnerability analysis into the pre-silicon stage of processor development.
The platform, now part of Arteris, identifies security-relevant behaviour within hardware designs, traces potential attack paths, and verifies whether implemented controls operate as intended. Security properties developed for one block or programme can be retained and reused, allowing established assurance work to follow processor technology into subsequent generations.
Modern CPUs combine privilege controls, debug functions, memory-protection mechanisms, cryptographic blocks, firmware interfaces, and third-party intellectual property. A weakness can emerge from the interaction between otherwise functional elements, particularly when an unexpected sequence of states produces access that was never intended by the architecture.
Conventional functional verification establishes whether a design produces the correct results under specified conditions, but it does not automatically reveal whether an attacker can manipulate control paths, bypass isolation, expose protected data, or reach a privileged state through an unusual sequence of events.
Hardware-security analysis examines those paths directly. Potential weaknesses include insecure reset states, unintended debug access, privilege escalation, information leakage, incomplete access control, and cases where a protection mechanism can be disabled or circumvented by another block.
Finding such faults before tape-out avoids the more restrictive choices available once silicon has been manufactured. Post-silicon mitigation may require firmware changes, disabled functions, altered operating modes, package revisions, or a new mask set, while customers must determine whether products already deployed can be updated without creating further risk.
Reusable properties become increasingly valuable as processor portfolios adopt modular architectures. CPU cores, coherent interconnects, memory systems, accelerators, security subsystems, and interface IP may be assembled differently across automotive, infrastructure, and embedded products, with each combination creating a new set of interactions.
Verification must therefore follow both the reused blocks and their changing context. A module that behaves securely in one system can become vulnerable when connected to a different bus, privilege structure, reset controller, or debug environment, so inherited assurance cannot replace system-level analysis.
European product-security rules are increasing the pressure to address those issues throughout development and support. Measures examined in recent European cyber and AI security work extend responsibility into vulnerability handling, update provision, risk assessment, and secure product engineering.
Although such requirements are generally expressed at product level, their implementation reaches into the processor architecture. Secure boot, protected key storage, root-of-trust functions, memory isolation, and authenticated updates all depend on hardware controls that remain effective when software has been compromised.
Chip complexity is broadening the verification surface. AI accelerators, chiplet interfaces, coherent links, advanced power states, and increasingly configurable memory systems introduce further boundaries across which data and privileges must be controlled. Third-party IP can shorten development schedules, but every imported block also brings assumptions that must be tested within the complete design.
Automated analysis is becoming necessary because simulation cannot exhaustively cover every internal state of a large system-on-chip, while specialist hardware-security teams remain comparatively small. Tools that rank attack surfaces and preserve reusable properties allow those teams to concentrate on paths with the greatest potential consequence.
Cryptographic development adds another layer. STMicroelectronics has integrated post-quantum security functions into mobile silicon, introducing algorithms intended to withstand future attacks from quantum computers. Their protection still depends on secure control logic, memory access, key handling, and data paths surrounding the cryptographic engine.
Arm’s licensing model increases the reach of any weakness that survives into a released core. A processor design can appear in many devices, each combined with different peripherals, memory maps, firmware, and threat environments, so common pre-silicon assurance provides a baseline before licensees add their own integration layers.
No verification platform can eliminate vulnerabilities introduced through firmware, manufacturing variation, electromagnetic leakage, physical probing, or later system integration. Moving architectural and implementation analysis earlier does, however, reduce the number of avoidable weaknesses carried into devices that can no longer be changed economically.
Expanding Radix across further CPU programmes embeds hardware-security sign-off more deeply within the design flow. Its effectiveness will be judged by whether reusable assurance remains valid across increasingly configurable architectures and whether the resulting evidence can support customers, assessors, and certification bodies after the processor enters production.
