Lotus Microsystems targets AI power density

Lotus Microsystems has launched vStrata, a vertical power delivery platform developed for high-current AI processors and dense data-centre compute systems.

The Copenhagen-based company’s first platform module, LSC0580, is scheduled to ship as engineering samples in Q3 2026. Built around silicon Power Interposer Technology, the module moves power conversion closer to the processor while treating electrical delivery, thermal behaviour, and mechanical integration as a single package-level problem.

AI accelerators are drawing thousands of amps at low voltage, leaving little margin for losses in the final stage of power delivery. Conventional board-level conversion and lateral power distribution can create voltage drop, transient response challenges, local heating, and congestion around the processor package.

vStrata shifts conversion vertically beneath the load. The architecture is designed to shorten the current path, reduce last-inch distribution losses, improve transient response, and release board area around the processor. Lotus Microsystems states that the LSC0580 module targets up to 96% point-of-load efficiency and can reduce power conversion losses by more than half against conventional approaches.

The module has been designed to fit into existing reference designs and power-management-controller environments. Integration compatibility is critical in AI infrastructure, where operators and hardware suppliers are trying to raise compute density without rebuilding entire platforms around every new accelerator generation.

The same pressure is visible farther up the electrical chain, where Siemens, NVIDIA, Fluence, and nVent have developed a reference architecture for AI data centres covering electrical distribution, controls, storage, and modular low-voltage systems. Lotus Microsystems is working closer to the processor, where package, board, and power-stage design now converge.

As accelerator power rises, every milliohm of distribution resistance and every millimetre of current path becomes more costly. Power electronics, substrate design, mechanical stack-up, and thermal modelling are being compressed into the same engineering space, with power integrity and cooling now influencing processor deployment as directly as compute performance.

Vertical power delivery has been explored for several processor generations, but adoption has been slowed by integration complexity, qualification demands, and thermal management. Bringing conversion beneath the load can improve electrical performance, yet it also concentrates heat and places stricter requirements on materials, assembly tolerances, serviceability, and validation.

vStrata reflects a broader movement in high-performance electronics, where the package is no longer passive infrastructure. Advanced AI processors, high-bandwidth memory stacks, interposers, optical links, and power modules are turning packaging into an active determinant of system performance. Electrical, thermal, and mechanical constraints are no longer late-stage layout issues; they are architectural limits.

Datacentre efficiency targets add further pressure. Power lost near the processor becomes heat that must be removed, raising the burden on cooling systems and reducing the useful compute density of a rack or facility. Compact, high-efficiency conversion at the point of load can improve both energy performance and physical utilisation, provided reliability and maintainability survive deployment at scale.

Engineering samples of LSC0580 will provide an early view of how far vertical power delivery can move from concept into production infrastructure. AI compute demand is still rising faster than the electrical and cooling systems built around it, and the next stage of accelerator scaling may depend as much on power architecture as on silicon performance.