IN Brief:
- Siemens and TSMC have enabled automated DRC fixing across digital and custom IC design flows.
- The agent combines Calibre verification with Aprisa implementation and Solido technologies.
- Wider enablement covers advanced packaging, thermal analysis, silicon photonics, and A14 process certification.
Siemens and TSMC have extended their semiconductor design collaboration with an AI-powered agent that can identify, analyse, and correct design rule check violations across digital and custom integrated circuit flows. The workflow links Siemens’ Calibre verification technology with Aprisa digital implementation and Solido design software.
Design rule checking is a mandatory stage before an IC can progress towards tape-out. Layout geometry has to comply with foundry rules covering dimensions, spacing, enclosure, connectivity, and process-specific constraints. Violations can require repeated diagnosis and correction as a design converges, particularly on advanced process nodes where rule decks are large and interactions between neighbouring structures become more complex.
Siemens says the new workflow builds on Calibre Check Assist, which supplies contextual information during DRC debugging. The AI agent adds the ability to reason across a violation, call connected EDA tools, make a correction, and evaluate the result. Aprisa supplies place and route functions for digital implementation, while Solido contributes AI and simulation capabilities used in custom IC development and design-space exploration.
The agent sits within Siemens’ Fuse EDA AI System and Fuse EDA AI Agent architecture. The company is positioning Fuse around long-running, self-verifying workflows that can coordinate tasks across more than one application. NVIDIA AI technology is also being used within the wider environment to support reasoning and execution.
Automating DRC correction is more demanding than producing a plausible layout edit. Removing one violation can create another, alter routing congestion, disturb timing, or affect power and signal integrity. Any automated fix therefore has to be checked against the wider implementation rather than accepted because the local geometry now satisfies a single rule.
The collaboration extends beyond DRC. Siemens has added multi-machine support in Calibre 3DStack Advanced for inter-chiplet antenna verification on TSMC-SoIC, while qualification work is continuing around CoWoS-L. The companies are also working on chip-package co-design, die-to-die autorouting, and interface checking for system-on-wafer designs, reflecting the growing verification burden created by heterogeneous integration.
Thermal and photonic design are part of the same enablement programme. Calibre 3DThermal has been certified for static and transient thermal analysis on TSMC A16 and is being applied to system-on-wafer and 3DFabric technologies. Siemens and TSMC are also developing design and verification flows around the foundry’s COUPE silicon photonics platform. TSMC’s current COUPE roadmap is increasing channel rates and heterogeneous integration for AI interconnects.
At process level, Calibre nmDRC, nmLVS, xACT, and PERC have been certified for TSMC A14. Solido Simulation Suite is certified for SPICE accuracy across N3C, A16, and A14, while mPower carries certification for transistor-level IR and electromigration analysis on N2P and N3C configurations. These approvals give the AI workflow access to qualified engines rather than asking a generative model to judge sign-off conditions independently.
Foundry qualification defines the limits within which the automation has to operate. A faster debugging loop is useful only if the resulting design continues to satisfy timing, electrical, reliability, and physical requirements. Connecting the agent directly to qualified analysis tools gives it a way to test each action against measured engineering constraints.
Siemens and TSMC have not said that DRC sign-off itself is becoming autonomous. Engineers still define the design intent, manage implementation trade-offs, and approve the final result. The automation is aimed at the repetitive diagnosis and correction cycle surrounding physical verification, where advanced nodes and multi-die systems continue to increase the number of interactions that have to be resolved.
The next evidence will come from large customer designs. If automated fixes can reduce debug time without increasing timing closure, congestion, or later verification work, the approach could remove a meaningful part of the iteration around advanced-node implementation. If the corrections simply move problems elsewhere, the gains will be far less substantial. The qualified TSMC flows now provide a practical environment in which that distinction can be measured.
