IN Brief:
- M31 and Ambiq have combined an SPSRAM memory compiler and standard-cell library for TSMC N12e.
- The memory architecture approaches 500MHz in low-power mode using a near-threshold peripheral supply.
- M31 reports approximately 50% leakage savings from the jointly developed standard-cell library, while full compiler development continues.
M31 Technology and Ambiq have developed an ultra low power Foundation IP package for TSMC N12e, combining an SPSRAM memory compiler with a standard cell library for always-on and edge AI systems. The work targets lower leakage and smaller area while retaining the performance needed for local processing.
Foundation IP sits beneath much of the application-specific functionality in a system on chip. Standard cells and compiled memories provide the basic implementation resources used across the design, so their density, leakage, voltage behaviour, timing, and process compatibility influence a large proportion of the finished die.
The memory element is an N12e ultra low leakage SPSRAM compiler supporting both high performance and ultra low power modes within the same physical memory footprint. M31 says the compiler includes redundancy, power gating, and built-in self-test, giving the memory production and reliability functions alongside its power management features.
A dual rail architecture allows the memory to operate close to 500MHz in low power mode while the peripheral circuitry runs near its threshold voltage. M31 also reports VCCA retention leakage at 1.05 to 1.1 times total bit cell retention leakage, indicating that the supporting memory circuitry has been designed not to dominate standby consumption when data are retained.
That balance is relevant in always-on devices because the memory subsystem remains active even when the main processor is doing little work. Voice triggers, sensor fusion, health monitoring, security functions, and local inference can leave a device waiting for events for long periods, making standby leakage a significant part of its energy budget.
The companion standard cell library was developed around Ambiq’s platform requirements. M31 says the collaboration combines Ambiq’s cascade-style low power approach with its own circuit and physical layout techniques and has produced approximately 50% leakage power savings at library level.
That figure does not translate directly into a 50% reduction for a complete SoC. Memories, analogue blocks, interfaces, clocks, power management, accelerators, and software-controlled activity all contribute to total consumption, but leakage reductions across heavily replicated standard cells can still affect a substantial portion of the digital logic.
Area is being addressed alongside power. Edge AI and AIoT devices increasingly combine local inference, security, connectivity, and larger firmware while remaining constrained by package size and cost. A smaller library or denser memory can reduce die area or free space for additional functions without automatically moving to a more complex packaging arrangement.
M31 says initial memory instances have shown favourable power, performance, and area results, while full compiler development is still under way. The announcement is therefore a Foundation IP development milestone rather than evidence of a complete Ambiq device already in volume production on the platform.
N12e is being used here to balance implementation maturity with low power behaviour rather than simply pursue the smallest process geometry available. In always-on systems, analogue integration, leakage, cost, design infrastructure, and predictable qualification can be as important as transistor density, particularly when the device has to remain powered from a constrained energy source.
Validated memory compilers and standard cell libraries can also reduce physical design work for a new SoC. Foundation IP provides characterised timing, layout, test, retention, and process information that would otherwise have to be created or qualified internally before the design can progress towards tape-out.
Ambiq has built much of its product positioning around energy-efficient edge processing, while M31 supplies memory compilers, standard cell libraries, and other reusable silicon IP across several foundry processes. Their N12e work moves that low power emphasis into the implementation layer beneath the processor and application blocks.
The next measure will come from completed compiler qualification and customer silicon operating across voltage, temperature, and process variation. Near-threshold operation and lower library leakage are useful results at IP level, but production value depends on whether those gains survive integration into SoCs that also have to meet timing, yield, reliability, and application performance targets.
