IN Brief:
- AURIX RC1 is Infineon's first RISC-V-based microcontroller platform, targeting automotive and other real-time control systems.
- Planned configurations include up to 12 32-bit cores, 40 MB embedded memory, and selected high-speed networking interfaces.
- A virtual prototype is available, while first silicon samples are targeted for the first half of 2027.
Infineon Technologies has introduced AURIX RC1, a new RISC-V-based microcontroller platform designed to support real-time control across software-defined vehicles, industrial equipment, and emerging robotics applications.
The architecture marks Infineon’s first adoption of RISC-V within its AURIX microcontroller range. It is intended to provide a common computing foundation for applications previously served by different controller families, combining scalable processor configurations with functional safety, cybersecurity, and high-speed communications.
Infineon will present the AURIX RC1 family concept at electronica in Munich from 10 to 13 November 2026. First silicon samples are targeted for the first half of 2027, while a virtual prototype is already available to support architecture evaluation and software development before physical devices become available.
Software-defined vehicle architectures are changing how computing resources are distributed across automotive electronic systems. Functions previously implemented by separate electronic control units are increasingly being consolidated into zone controllers, central computers, and systems responsible for several vehicle domains.
Such consolidation creates competing processing requirements. A controller may need to execute time-critical operations associated with vehicle dynamics or power conversion while handling communications, diagnostics, software management, and other functions that operate on different schedules.
Real-time performance depends on more than the maximum processing speed of an individual core. Memory access, interrupt handling, scheduling, resource sharing, and communications latency can determine whether an application completes its required operations within a defined time interval.
AURIX RC1 addresses these requirements through a modular RISC-V architecture intended to scale across different processing configurations. The company plans devices incorporating up to 12 32-bit processing cores, an advanced parallel processing unit for edge AI workloads, and as much as 40 MB of embedded memory.
These specifications describe the planned product family’s upper configurations rather than a single commercially available component. Infineon has also outlined a higher-end product line that will add 64-bit microprocessor capabilities, extending the architecture beyond conventional microcontroller applications.
Different processing resources can be assigned to tasks with different computational and timing requirements. A real-time controller may supervise actuators and monitor safety conditions while a more capable processing subsystem handles complex application software or analytical functions.
The effectiveness of such an arrangement depends on the available memory protection, scheduling mechanisms, peripheral architecture, and the interaction between processing domains. Simply integrating more cores does not establish deterministic response times when several software workloads compete for shared resources.
Infineon intends AURIX RC1 to span body and chassis control, powertrain systems, battery management, safety functions associated with driver assistance, cockpit applications, and vehicle networking. The new range combines capabilities previously associated with the company’s AURIX and TRAVEO T2G microcontroller families.
RISC-V provides a common instruction set architecture that can be implemented across processor designs with different performance and peripheral requirements. Its modular structure allows Infineon to configure processing resources for particular applications while maintaining elements of a shared software foundation.
A common instruction set can assist software portability, but it does not remove every difference between devices. Peripheral interfaces, safety architectures, memory arrangements, operating systems, and device-specific drivers will continue to influence the effort required to migrate an application.
Infineon is developing the DRIVECORE software ecosystem to address these requirements. It combines software from the company and external partners into integrated development packages supporting AUTOSAR, open-source software, functional safety, and cybersecurity.
Virtual prototyping provides an early development route before physical silicon is available. Engineering teams can begin evaluating software architecture, integration requirements, and selected application workloads using a virtual representation of the intended hardware.
Virtual validation cannot replace testing on production-representative devices. Electrical behaviour, final timing performance, thermal characteristics, and hardware fault responses must still be established through later development and qualification activities.
Functional safety is a central part of the planned architecture. Infineon states that AURIX RC1 is designed to support automotive applications up to ASIL D, the highest Automotive Safety Integrity Level defined within ISO 26262.
Achieving the required safety integrity involves the complete system, including diagnostic coverage, software development, hardware failure analysis, fault handling, and verification against allocated safety requirements. An MCU designed for ASIL D applications does not independently establish that every system incorporating it will satisfy that classification.
Cybersecurity mechanisms are also being incorporated into the platform. Infineon identifies hardware protection, cryptographic agility, and support for requirements associated with ISO/SAE 21434 and the European Cyber Resilience Act.
The architecture is intended to accommodate future cryptographic changes, including requirements associated with post-quantum cryptography. The announcement does not establish that every planned security mechanism has completed qualification or that all future regulatory requirements have already been met.
Communications support includes CAN-XL, 10BASE-T1S, and multi-gigabit Ethernet, allowing the family to address different vehicle network architectures. These interfaces serve distinct functions, from communication among local control devices to higher-bandwidth data exchange between larger computing systems.
Selected AURIX RC1 configurations will incorporate Infineon’s BRIGHTLANE Ethernet switching technology and hardware-accelerated routing. Integrating network switching can reduce the need for a separate switching component in suitable designs, while hardware routing can reduce the processing resources required to manage particular data transfers.
The completed network architecture must still account for bandwidth allocation, packet timing, redundancy, and the behaviour of the control system during communications failures. Integrated networking capability does not remove those system-level engineering requirements.
Power management is another part of the platform, with Infineon developing corresponding OPTIREG supply solutions. Multiple processing domains and operating modes create opportunities to reduce energy consumption when portions of the system are inactive, although the achievable savings will depend on application activity and the selected device configuration.
Peter Schiefer, President of the Automotive Division at Infineon, said: “Microcontrollers need to become more configurable, scalable, and adaptable while maintaining highest safety and security levels as applications evolve.”
Infineon is also working through RISC-V International and Quintauris to support the development of automotive RISC-V software, tooling, and interoperability. The wider ecosystem will influence how readily manufacturers can migrate applications between processors and obtain suitable development, diagnostic, and safety software.
The immediate development programme centres on the AURIX RC1 virtual prototype, software integration, and preparation for first silicon in 2027. Device-level qualification, production availability, and the performance of completed automotive implementations remain to be established as the family progresses towards commercial deployment.
