Beijing launches three-year AI4Chip programme

Beijing launches three-year AI4Chip programme

Beijing has launched a three-year AI4Chip semiconductor industry development programme. The plan applies artificial intelligence across IC design, wafer fabrication, packaging, test, equipment, materials, and supporting engineering infrastructure.


IN Brief:

  • Beijing E-Town's 2026–28 programme contains five actions and 20 priority tasks across the semiconductor value chain.
  • AI is targeted at design, fabrication, packaging, test, equipment development, materials, and industrial data.
  • The district wants 3–5 internationally influential AI4Chip ecosystem companies and more than ten benchmark applications by 2028.

Beijing Economic-Technological Development Area has launched a three-year AI4Chip programme intended to apply artificial intelligence across the integrated-circuit development and manufacturing chain, covering design, wafer fabrication, packaging, test, semiconductor equipment, materials, and supporting industrial infrastructure.

The 2026–28 action plan sets out five main actions and 20 priority tasks, with the district aiming to establish an integrated semiconductor and AI development system by 2028. Targets include cultivating three to five internationally influential AI4Chip ecosystem companies and creating more than ten benchmark applications capable of wider industry use.

The programme goes beyond using generative AI as a design assistant. Beijing E-Town is targeting circuit design, verification, physical implementation, process optimisation, production control, packaging, test, equipment development, and materials. The policy describes AI4Chip as embedding artificial intelligence into the semiconductor value chain to reduce reliance on manual experience and physical trial-and-error.

Chip design is one of the more mature areas for that approach because EDA flows already use optimisation techniques to explore placement, routing, timing, power, and verification spaces that would be impractical to search manually. Extending AI further into IP generation, physical design, and verification could reduce iteration, but engineering sign-off still depends on deterministic constraints, traceability, and reproducible results.

The manufacturing side is less forgiving. Semiconductor fabs generate large volumes of process, equipment, defect, and metrology data, but models used in production have to operate inside narrow process windows and survive changes in wafers, tools, materials, chamber histories, and maintenance states. A correlation that looks useful during development can become expensive if it drives the wrong adjustment on a production line.

Beijing E-Town’s plan therefore links AI deployment with industrial datasets, models, computing resources, and demonstration projects. It also calls for AI-enabled wafer production, intelligent packaging and test, equipment development, and closer interaction between design and manufacturing data. That matters as advanced products increasingly depend on chiplets, three-dimensional integration, high-bandwidth memory, silicon photonics, and power-delivery constraints that cut across traditional design boundaries.

The policy names areas including GPUs, AI training and inference ASICs, RISC-V processors, high-end CPUs, memory, silicon photonics, electrical interconnects, server power devices, and FPGAs. It also points to compute-in-memory, three-dimensional stacking, and combined sensing and communications as development directions, placing the programme close to the architectures driving current AI and high-performance computing investment.

For equipment suppliers, digital twins and machine-learning models could reduce physical experiments during tool development or help identify drift before yield is affected. The practical limit is explainability and transferability: process engineers need to know whether a model remains valid when recipes, chambers, materials, or device structures change. Semiconductor manufacturing tolerates very little ambiguity when a decision can affect thousands of wafers.

Packaging and test are another logical target because they generate their own measurement and inspection data. As packages become more complex, AI could assist defect classification, equipment tuning, test optimisation, and yield learning, but only if data from assembly, inspection, electrical test, and upstream wafer processes can be connected reliably.

Beijing E-Town says it already hosts more than 400 integrated-circuit companies with an industry scale above RMB130 billion, spanning design, wafer manufacturing, packaging and test, equipment, components, and materials. That concentration gives the programme access to several parts of the semiconductor data chain, although commercial sensitivity and incompatible data structures will make cross-company integration difficult.

The three-year timetable is ambitious, particularly where the policy moves from software assistance into process and equipment control. Success will be easier to judge through engineering outcomes than through the number of AI tools deployed. Shorter verified design cycles, improved equipment productivity, lower process variation, better defect detection, and higher yield would all provide harder evidence that AI4Chip is changing semiconductor development rather than simply adding another layer of software to it.


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