Microchip launches plug-in timing module for AI servers and 5G vRAN

Microchip has introduced the MD-990-0011-B family of plug-in timing modules for data-centre servers and 5G virtualised radio access network platforms, packaging high-precision synchronisation, holdover capability, and supporting timing functions into a modular card for easier integration into server architectures.

Developed in collaboration with Intel and designed for Intel Xeon 6 SoC-based server platforms, the MD-990-0011-B family supports automatic source selection and locking across GNSS, Synchronous Ethernet, and Precision Time Protocol. Two variants are being offered: the MD-990-0011-BC01 with up to eight hours of holdover performance, and the MD-990-0011-BA01 with up to four hours. The family is aimed at cloud, virtualisation, and high-availability deployments where synchronisation integrity is becoming a visible system requirement.

The modules consolidate a SyncE synthesiser with dual DPLL channels, oven-controlled crystal oscillators for holdover, a temperature sensor, EEPROM-based board configuration support, and low-jitter timing circuitry. By assembling those functions into a plug-in module rather than leaving them to a custom timing subsystem on the main board, the design shortens integration work, simplifies upgrades, and reduces maintenance overhead in platforms that may need to support different synchronisation profiles over time.

Timing is becoming harder to ignore in AI data centres and virtualised 5G networks. In vRAN, accurate time and frequency distribution remain essential to coordinated radio behaviour and low-latency operation. In modern server environments, especially those supporting distributed workloads and acceleration, clock integrity increasingly shapes how reliably systems coordinate across the platform.

Plug-in timing modules are one response to that pressure. Instead of forcing every server design team to implement and validate a bespoke timing chain, the module model treats synchronisation as a deployable subsystem. That is attractive not only for OEMs and ODMs looking to reduce board-level complexity, but also for operators who want more straightforward replacement and upgrade paths in deployed systems.

Holdover capability is a key part of that equation. GNSS remains useful, but external timing references are not always guaranteed and network conditions are not always stable. Strong holdover performance allows the platform to ride through disruption without an immediate collapse in timing accuracy. In telecom networks that is well established. In AI infrastructure, where synchronisation is intersecting with denser compute clusters and more distributed system behaviour, the same resilience is becoming more relevant.

There is also a broader architectural shift behind this class of product. The move toward disaggregated infrastructure, virtualised networking, and AI-ready server designs has pulled more specialist functions into modular hardware blocks. Storage, acceleration, security, and networking have all moved in that direction. Timing is now following.

For electronics designers, that makes timing more visible in the bill of materials, the thermal budget, the maintenance model, and the system roadmap. In data centres and 5G infrastructure, the acceptable margin for latency, drift, and synchronisation failure is narrowing. Timing hardware is no longer a quiet dependency sitting off to the side of the platform.

Microchip’s timing portfolio has long served markets where resilience and accuracy are inseparable. What is changing is the range of platforms that now need those qualities delivered in a form that can be integrated quickly and maintained easily. AI servers and virtualised radio systems are among the clearest examples, and both are likely to keep pushing timing higher up the design stack.