IN Brief:
- AttoTude reports a greater than 50% reduction in IC design cycles using Keysight EDA.
- Its ASICs over Dielectric work spans 200G, 400G, and 800G per-lane designs across 100GHz to 3THz.
- Shared design data and simulation-to-measurement correlation support sub-six-week tape-outs and reported first-pass silicon.
Keysight Technologies says AttoTude has cut IC design cycles by more than 50% after expanding Keysight EDA software across its development workflow. The interconnect company reports moving advanced RF, sub-THz, and THz designs from concept to tape-out in less than six weeks while repeatedly achieving first-pass silicon.
AttoTude is developing ASICs over Dielectric interconnect technology for AI and hyperscale data centre systems, with integrated circuits supporting per-lane data rates of 200G, 400G, and 800G. Its on-chip interconnects behave as waveguides, pushing electromagnetic modelling and layout accuracy into a frequency range that extends from 100GHz to 3THz.
The company is using Keysight Advanced Design System across the flow, supported by design data management software that maintains a shared, version-controlled environment. Engineers working in parallel on RF, sub-THz, and THz subsystems can keep layouts, electromagnetic models, simulation data, and revisions aligned rather than reconciling separate design states late in the programme.
At those frequencies, interconnect geometry and dielectric behaviour form part of the circuit rather than sitting downstream as packaging detail. Parasitics, coupling, material properties, and physical layout can alter performance enough to undermine a design that appears acceptable in a more abstract simulation. Electromagnetic analysis therefore has to remain tied to the layout that will actually be fabricated.
Keysight says AttoTude also uses system-level scenario planning to explore design trade-offs before committing to silicon, while simulation-to-measurement correlation is used to compare models with fabricated devices. First-pass success depends heavily on that feedback loop because subsequent design decisions become more useful when measured silicon tracks the behaviour predicted during simulation.
Richard Chan, ASIC architect and development leader at AttoTude, said the software had helped the engineering team “move faster with greater confidence” while maintaining first-pass silicon success. The result applies to AttoTude’s own designs and workflow, but it gives a measurable example of the relationship between data control, electromagnetic simulation, and semiconductor schedules.
The deployment follows Keysight’s wider push towards reusable EDA workflows. Earlier this year, the company added executable workflow capture to its RF design software, allowing simulations, optimisation routines, decision trees, parameters, and editable Python to be preserved as repeatable engineering processes. AttoTude’s tape-out work applies the same principle to a live high-frequency silicon programme.
Shorter development cycles carry particular value in advanced interconnects because a respin consumes much more than another wafer. Layout changes have to be reverified, masks and fabrication repeated, packaged devices returned for measurement, and the wider system programme held while engineers establish whether the revised silicon solves the original problem.
High-frequency devices also create more opportunities for model error to propagate. Package transitions, on-chip transmission structures, process variation, temperature, and measurement fixtures can all affect the correlation between simulation and hardware. A shared design environment cannot remove those physical effects, but it can make it easier to trace which model, layout, and parameter set produced a particular result.
AI infrastructure is simultaneously pushing higher bandwidth between processors, memory, and networking devices. Increasing per-lane data rate can reduce the number of lanes needed for a given aggregate bandwidth, but it raises signal-integrity and electromagnetic demands on each channel, particularly as electrical interconnects move further into millimetre-wave and terahertz operation.
AttoTude’s sub-six-week tape-out cycle is a useful benchmark rather than a general development timetable. Design size, verification burden, process technology, packaging, and qualification all affect cycle length. The more significant result is that the company reports repeated first-pass silicon while compressing the workflow — speed accompanied by measured correlation rather than speed recovered through another respin.
