IN Brief:
- Neoverse CSS N4 supports up to 128 cores per die, LPDDR6 memory, and PCIe Gen 7.
- Arm claims up to twice CSS N3 performance, 1.25x performance per watt, and 1.75x memory bandwidth.
- The subsystem is intended as a configurable foundation for custom compute, DPU, networking, and other infrastructure silicon.
Arm has introduced Neoverse Compute Subsystems N4, a configurable infrastructure platform supporting up to 128 cores per die, LPDDR6 memory, and PCIe Gen 7 connectivity. The subsystem is intended to give semiconductor companies a pre-integrated foundation for custom compute, DPU, networking, and other specialised infrastructure designs without requiring every part of the CPU subsystem to be assembled independently.
Compute Subsystems sit between licensing individual processor IP blocks and buying a finished processor. Arm supplies a larger, validated collection of CPU, coherent interconnect, memory, I/O, implementation, and software-enablement technology, while the customer retains scope to customise the surrounding silicon for its target workload.
CSS N4 is Arm’s most configurable Neoverse CSS so far. The company describes it as its fastest path from a CSS starting point to finished silicon, reflecting an effort to reduce integration and verification time for organisations that want a differentiated chip but do not want to construct the entire server-class CPU subsystem from discrete IP.
Arm claims up to twice the performance of Neoverse CSS N3, up to 1.25 times the performance per watt, and up to 1.75 times its memory bandwidth. Those figures are Arm comparisons rather than independent benchmarks and will ultimately depend on the customer’s implementation, process technology, memory configuration, workload, and power envelope.
The I/O and memory changes are as important as the core count. PCIe Gen 7 is aimed at a new generation of accelerator, network, and storage connectivity, while LPDDR6 provides another route to high bandwidth with power consumption suited to dense infrastructure designs.
Those interfaces reflect the way data-centre CPUs increasingly operate alongside accelerators rather than as isolated compute engines. Processor cores handle system services, orchestration, storage, networking, agent execution, and control-plane work while large volumes of data move between memory, accelerators, network interfaces, and other nodes.
Up to 128 cores per die gives system designers room to build throughput-oriented devices, but CSS N4 is not a finished 128-core processor that every customer will deploy unchanged. The configurable subsystem is intended to support different silicon products, from scale-out compute devices to DPUs and specialised networking platforms.
Arm is positioning that option alongside its AGI CPU rather than as a replacement for it. Customers that want greater silicon differentiation can begin from CSS N4, while organisations seeking a production-ready processor can use the AGI CPU platform. Both sit within the Neoverse architecture and software ecosystem, but they involve different levels of customer design responsibility.
The model reflects a wider expansion of custom infrastructure silicon beyond a small group of hyperscale operators. DPUs, smart NICs, storage processors, networking devices, and workload-specific compute platforms are becoming more common as system designers try to optimise power, data movement, and rack-level throughput around particular deployments.
The difficult work in such devices extends beyond choosing a CPU architecture. Coherent interconnect, memory controllers, high-speed I/O, firmware, verification, physical implementation, packaging, and software bring-up all have to converge before tape-out. A larger pre-integrated subsystem can remove some of that repeated engineering while still allowing differentiation around the remaining system.
Earlier verification work around Arm’s AGI CPU has already shown the role of pre-silicon validation in large infrastructure processors, where coherent interconnects, interfaces, firmware, and software have to be exercised well before working silicon is available.
Arm’s Total Design ecosystem extends that approach across IP, EDA, foundry, packaging, firmware, and software partners. CSS N4 gives the ecosystem another standardised hardware foundation, but customer tape-outs will determine whether the claimed development-time reduction and performance gains translate into production devices.
The launch therefore adds a more configurable route into the Neoverse portfolio rather than another general-purpose server processor. The engineering test will come when customers disclose their first N4-based silicon, including which parts of the subsystem they retained, what they customised, and how the resulting power, bandwidth, and throughput compare with less integrated design approaches.
