Category: News
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Palomino has completed its acquisition of interconnect developer Vega Links. The combined company plans copper and optical chipsets for expanding AI clusters.
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NEO has combined two memory concepts for future AI processors. X-SRAM targets denser on-chip storage while 3D X-DRAM addresses external memory capacity.
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Actions and Ceva have integrated Bluetooth HDT into audio silicon. ATS296X devices target lossless multichannel sound, lower latency, and faster wireless updates.
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Silicon Labs has combined Bluetooth 6 ranging with industrial interfaces. BG2B adds CAN FD, dual ADCs, LED control, low-power conversion, and hardware security.
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GE Appliances will integrate Texas Instruments chips into connected laundry. US-made processors, wireless devices, and analogue components will support production beginning in 2027.
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Microchip and Micron linked PCIe 6 switching with production SSDs. The FMS demonstration targets scalable storage for AI, cloud, and high-performance computing systems.
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SK hynix and Sandisk have published initial HBF interface specifications. Capacities reach 512GB while three bandwidth grades span approximately 0.4TB/s to 3.0TB/s.
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Renesas restarted phased wafer production at Kawashiri one day early. Pre-earthquake input capacity is targeted within approximately three weeks.
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Alif has licensed Keil MDK for its embedded AI families. The agreement adds Arm-native development, debug, middleware, and simulation support across Ensemble and Balletto devices.
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Researchers moved one spin qubit across four isolated silicon registers. The five-qubit processor completed weight-four parity checks required by surface-code error correction.