Category: Design engineering
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Rapidus has signed a UK agreement on semiconductor manufacturing collaboration. The MoU links UK semiconductor strategy with Japan’s advanced 2nm logic manufacturing plans.
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Synopsys has released Multiphysics Fusion tools for chip design closure. The flows integrate timing, power, thermal, electromagnetic, multi-die, analogue, and photonic analysis.
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Xiphera is joining Finland’s SecureSoC programme for trusted semiconductor systems. The project links hardware cryptography, RISC-V design, AI-assisted verification, and supply-chain resilience.
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Legacy aerospace and satellite platforms face rising connectivity demands. Filtronic CTO Tudor Williams explains how solid-state power amplifiers can replace travelling wave tube amplifiers, improving reliability, reducing maintenance, and enabling higher-throughput links without the cost and complexity of full platform redesigns.
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Agile Analog and Xiphera are joining physical and cryptographic protection. Their collaboration combines anti-tamper sensor IP with post-quantum cryptographic cores.
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Keysight has expanded RF analysis options for wideband validation work. The XA5 and XA6 platforms target wireless, radar, and spectrum operations.
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Murata has added component models to Ansys simulation workflows directly. The Ansys-compatible files cover RF inductors, MLCCs, and power inductors.
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Commercial UAV production is creating new pressures on battery development strategies. As manufacturers move from low-volume engineering programmes to repeat production, battery packs must deliver more than performance alone, requiring manufacturability, traceability, testing rigour, and supply chain resilience to support sustainable growth.
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Menta and Presto are taking reconfigurable logic into ASIC flows. Their collaboration pairs embedded FPGA IP with industrialisation support for long-lifecycle semiconductor programmes.
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NGMN has outlined operator-led guidance for future 6G migration. The papers emphasise spectrum sharing, device readiness, chipset maturity, RF front-end design, and power efficiency as deployment constraints.