Category: Design engineering
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Singular Photonics has launched Litavis, a programmable multimodal SPAD sensor. The Edinburgh-developed device combines photon counting, timing, histogramming, and in-pixel processing within one configurable imaging platform.
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Leader has launched two handheld instruments for 12G-SDI signal testing. The Sx2E adds real-time eye-pattern and jitter analysis for development, commissioning, and fault diagnosis across SDI interfaces.
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Fujitsu and Yaqumo are testing quantum software on neutral-atom hardware. Physical trials will assess whether Fujitsu’s STAR architecture and open operations toolchain can transfer from superconducting-system development onto Yaqumo’s ytterbium-based platform.
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Quantinuum has secured $100 million for quantum manufacturing research programmes. GlobalFoundries will fabricate next-generation ion traps and electronics using 300mm wafer technology while Monarch Quantum develops scalable laser and optical hardware for trapped-ion systems.
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Xanadu and ASML will refine lithography for photonic quantum hardware. The collaboration will examine line-edge roughness, patterning control, and optical loss as Xanadu works towards repeatable fabrication for fault-tolerant, error-corrected quantum systems.
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Samsung and Mistral will deploy on-premises AI across semiconductor operations. The partnership targets defect analysis, equipment optimisation, development cycles, manufacturing precision, and yield stability while keeping sensitive process data within Samsung infrastructure.
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IonQ has moved Superion 256 towards semiconductor-based quantum manufacturing scale. Integrated 256-qubit QPUs are fabricated, with first ions trapped in prototypes.
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Qualcomm and Amazon are collaborating on custom AI silicon platforms. The programme also covers optical connectivity extending to 1.6T.
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Arm has expanded Neoverse with its configurable CSS N4 platform. The subsystem supports 128 cores, LPDDR6 memory, and PCIe Gen 7.
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French researchers have combined memristors and SMTJs for hardware optimisation. The architecture uses device-level randomness to implement intrinsic annealing during its search.