Category: Design engineering
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Rapidus and HCLTech have opened Indian semiconductor development centres together. The Bengaluru and Hubli facilities will support mask design, process design kits, and layout work for advanced manufacturing.
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Rohde and Schwarz will introduce two instruments at electronica 2026. The handheld combi analyser combines RF measurement modes, while the HMP5050 offers five independent bench-supply channels.
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Luxonis has developed modular hardware for multichannel embedded vision applications. The OAK 4 FFC board is intended for system builders integrating several camera channels into robotics and machine equipment.
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SkyWater is offering quantum photonics startups new semiconductor foundry access. OnRamp provides engineering roadmaps and conditional access to SP90 silicon nitride photonics development runs.
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Infineon is embedding silicon carbide devices directly within inverter boards. Its ENDOPACK concept targets lower parasitics and a different manufacturing route for automotive power stages.
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IQE and Atomera have agreed joint RF semiconductor development work. The companies will optimise gallium nitride epitaxy on silicon incorporating Mears Silicon Technology, with wafer samples intended for future customer evaluation.
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Rambus is adopting ChipAgents across its semiconductor design workflows companywide. The collaboration covers chip and silicon IP development, verification, and AI-assisted integration in existing electronic design automation environments.
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Glasgow researchers will lead a new UK electronic materials network. The £1.4 million RaRE initiative connects more than 50 partners working on semiconductor processing, electromagnetic materials and sustainable electronics.
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Cadence has opened sovereign infrastructure for European semiconductor design workloads. Its Munich OnCloud service is available now, with further NVIDIA computing systems and digital twin instances planned.
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Tenstorrent has released reusable infrastructure for open chiplet integration projects. The beta includes hardware security, system management, debug interfaces and an AXI4-over-UCIe bridge, whose public RTL remains at evaluation quality.