Tenstorrent releases Open Chiplet Atlas Harness

Tenstorrent has released an open source beta of the Open Chiplet Atlas Harness, supplying reusable hardware designs for security, startup, management, debugging and communication between semiconductor dies. The framework provides reference implementations for functions that chiplet developers would otherwise need to build and integrate themselves, although the released hardware remains subject to further verification before use in finished silicon.

The Harness implements parts of the Open Chiplet Atlas architecture, which defines how chiplets from different suppliers can communicate and be managed within a system in package. Its specification covers several layers, including software, system management, protocols, transport and physical connectivity. Providing a common interconnect is only one part of that arrangement: separate dies must also establish their identities, initialise safely and respond consistently to management operations.

Tenstorrent’s beta contains register-transfer level, or RTL, descriptions for three principal management subsystems. The Security Processor provides a hardware root of trust, with functions for secure boot, measurement, key management and lifecycle control. These mechanisms support verification of firmware and configuration information before a system enters normal operation, but their effectiveness in a final chip also depends on secure provisioning, protected key storage and the implementation of the surrounding design.

The System Management Controller handles system bring-up, clocks, power and thermal management, reset coordination and telemetry. It also implements boot and configuration protocols defined by the Open Chiplet Atlas architecture for communication with other chiplets. A system assembled from several independently designed dies needs these functions to operate in a predictable sequence: a processor cannot reliably exchange information with an accelerator that remains in reset or has not completed its own configuration.

Tenstorrent brings the controller and security functions together through the Open Chiplet Atlas System Management Unit. The Harness also includes Debug and Test Ports, providing access through JTAG and support for cross-trigger debugging. Such facilities allow an investigation to follow relevant events between hardware blocks and chiplets rather than treating each die as an isolated component. They still require suitable access controls and integration with the debug facilities of the final system.

Communication across the package is supported by the project’s AXI-over-UCIe implementation, known as AoU. It carries native AXI4 transactions across Universal Chiplet Interconnect Express die-to-die links. AXI4 is used to move transactions between processing and peripheral blocks, while UCIe defines interfaces for communication across dies in a shared package. The bridge is intended to carry the former over the latter, allowing an AXI-based design to connect with functions implemented on another chiplet.

The separately maintained AoU repository offers a wrapper with a UCIe flit-die interface bring-up controller and another integration option for systems that manage that process externally. These alternatives affect how the bridge is incorporated into a chiplet’s link-control design. They do not establish compatibility with every physical implementation or remove the need to verify timing, reset behaviour, transaction handling and the electrical interface of the package.

The repository explicitly describes AoU as a pre-release design of evaluation quality. Its interfaces, registers and internal architecture may change before version 1.0, and full verification closure has not been completed. The availability of public RTL therefore gives semiconductor teams material they can examine and prototype with; it is not evidence that the bridge has been qualified for production, meets every interoperability requirement or has been validated in an unrestricted range of multi-die combinations.

Alongside its hardware descriptions, Tenstorrent has made a C++ and SystemC virtual platform available for firmware development before RTL simulation or physical silicon. The separate model repository documents environments for the Security Processor, the System Management Controller and their combined management unit. Developers can exercise startup sequences, register access and interactions between simulated subsystems while the hardware implementation is still being developed.

These are software models rather than complete substitutes for hardware verification. Transaction-level simulation can help identify errors in register programming, subsystem coordination and firmware assumptions, but does not by itself establish electrical behaviour, silicon timing or final power consumption. Tenstorrent’s documentation also identifies modelled and unmodelled functions, so test coverage must be considered when interpreting a result obtained on the virtual platform.

The public Harness repository contains the RTL, register descriptions, technical documentation and integration tooling. Its supporting resources include register-generation and verification workflows intended to make the design easier to inspect and adapt. The main code is published under Apache 2.0, while documentation and images carry a separate Creative Commons Attribution 4.0 licence; third-party notices also apply. Those terms allow reuse subject to their conditions, but open availability should not be confused with completed engineering qualification.

BOS Semiconductors contributed the original AXI-over-UCIe RTL, and lowRISC helped Tenstorrent make the Harness open source. VNChip Labs and Signaloid are identified as ecosystem partners whose contributions remain in progress. Their participation should not be represented as evidence that the beta already contains completed implementations from every named partner or has passed cross-vendor production interoperability testing.

Tenstorrent says common infrastructure can reduce non-recurring engineering costs and the risks associated with integrating several chiplets. It has not published a measured cost reduction or a benchmark comparing finished systems built with and without the Harness. The immediate benefit is access to reference designs and development tools that can be assessed within a particular semiconductor programme, with the final integration and verification responsibilities remaining with that programme’s engineers.

The beta is intended for early adopters, integrators and contributors, with a full release targeted for January 2027. Before a chiplet system can enter production, its designers will still have to validate the implemented security functions, management sequences, interconnect traffic and debug controls together with the physical package. Tenstorrent’s published development schedule provides a target for the software and RTL release, not a date on which every prospective chiplet combination becomes qualified.