Category: Processors
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MemryX and Lenovo are expanding Saudi sovereign edge AI deployments. Their platform combines ThinkEdge servers with Cascade 100P accelerators to process video and sensor data locally across infrastructure and industrial applications.
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Ambarella has launched its first standalone edge AI accelerator chip. X7 connects to Arm or x86 hosts through PCIe Gen 3 or USB 3.2 and is sampling alongside an M.2 reference design.
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Arteris has expanded its chiplet interconnect portfolio for multi-die designs. FlexGen Multi-Die extends non-coherent network-on-chip functions across UCIe links while preserving traffic control, quality of service, and design reuse.
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Cadence Tensilica IP drives Analog Devices’ next SHARC processor architecture. The SHARC-FX core moves ADI’s automotive DSP platform to 16nm while adding higher performance, AI processing, security, memory, and connectivity capabilities.
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Signaloid plans chiplet versions of its UxHw stochastic accelerator technology. Open Chiplet Atlas participation follows tapeout of its dedicated C0 ASIC.
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Axelera AI has launched Europa for enterprise inference deployments today. The 629-TOPS accelerator is shipping in validated Dell and Supermicro systems.
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EUCLYD has raised over €200 million for AI infrastructure development. The Eindhoven company is combining ASIC compute, memory, packaging, and rack-level design.
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Renesas has expanded its RZ/G family with two scalable MPUs. RZ/G3L and RZ/G3SE combine Cortex-A55 processing, Cortex-M33 control, industrial connectivity, and low-power Linux standby on a pin-compatible hardware platform.
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d-Matrix is integrating Raptor XPUs with NVIDIA NVLink Fusion infrastructure. The inference processor will enter MGX rack architecture alongside NVIDIA compute, networking, and data-processing components.
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Chinese AI-chip suppliers are raising prices as HBM shortages intensify. Huawei, Cambricon, and smaller accelerator developers face higher memory procurement costs, restricted supply, and increasingly difficult allocation decisions.