Category: Processors
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BrainChip has introduced Sequora processor IP for embedded sequence processing. Its state-space architecture is intended to limit context-related memory growth while supporting generative models on selected edge hardware.
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d-Matrix has begun shipping multi-rack Squadron systems for AI inference. The architecture scales Corsair accelerators through networked air-cooled racks and has demonstrated a mixed GPU-XPU pipeline for a defined language model.
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Lightmatter has demonstrated two optical systems for accelerator rack interconnects. The switch and compute trays use separate collaborations and Open Compute Project-aligned hardware.
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Marvell has introduced two six-channel CXL memory expansion controller designs. Structera X 3406 and 3506 support DDR4 or DDR5 respectively, adding PCIe 6.0 host connections, multi-host sharing and compression ahead of planned sampling in 2027.
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Cisco has introduced new switching silicon for dense AI networks. The G302 provides 51.2T aggregate switching capacity and 200G SerDes interfaces, with 1.6T optical connectivity in associated systems and customer shipments planned before the end of 2026.
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Microsoft has detailed chiplet architecture for its Maia 300 accelerator. The forthcoming inference system combines HBM4, locality-aware memory control and a 96-accelerator rack, with production deployment planned for 2027.
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Astera Labs unveils PCIe seven interconnect portfolio spanning optical links. Aries 7 combines retimers, redrivers and optical components, with initial customer sampling planned for late 2026.
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XMax agrees to acquire developer of vertical gallium nitride technology. The proposed Hexa Creation transaction centres on 1,200 V power semiconductor development rather than currently qualified commercial devices.
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Xsight introduces programmable data processor designs for lower-power network infrastructure. The E1L family includes an eight-core 100 Gbps configuration with a 25 W thermal design power.
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BOS Semiconductors joins Japanese research into automotive chiplet interconnect technologies. The South Korean semiconductor developer will contribute SoC and chiplet design expertise to MIRISE Technologies’ research and prototyping programme for future vehicle computing architectures.