Category: Processors
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STMicroelectronics and NUS have opened a four-year edge-AI research laboratory. HELIX will develop memory-centric architectures, accelerators, and silicon implementations for physical AI.
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India’s C2S programme has expanded practical semiconductor design training nationwide. More than 68,000 students have been trained, while 254 chip designs have reached tape-out.
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TIER IV and Renesas are combining software with automotive silicon. Autoware and reference AI models will run on R-Car Gen 5 hardware across assisted and autonomous driving applications.
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Socionext is extending its custom SoC roadmap to Intel 18A-P. Its first development is a high-performance compute chiplet targeting AI, HPC, edge, and data-centre systems.
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Neuromorphyx has launched BrainBoard1500 around BrainChip’s AKD1500 neural accelerator silicon. The compact board adds SPI/QSPI connectivity, Arduino Nicla compatibility, onboard model storage, and real-time power measurement.
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NXP has launched MCX A5 microcontrollers for secure industrial Ethernet. The family combines 10BASE-T1S topology discovery, post-quantum cryptography, and Arm Cortex-M33 processing up to 240MHz.
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NXP has launched MCX A5 microcontrollers for secure industrial Ethernet. The Cortex-M33 family integrates 10BASE-T1S digital PHY capability, topology discovery, and post-quantum security while targeting long-life industrial edge nodes.
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TIER IV is opening its autonomous-driving AI chip designs publicly. The JST-backed programme combines dedicated Transformer acceleration, open compiler tooling, and formal verification for edge systems.
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LX Semicon has begun mass production of its automotive MCU. The 40MHz Cortex-M3 device will enter Hyundai and Kia vehicles after around three years of development, qualification, and supply-chain preparation.
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Researchers have demonstrated a 28nm SRAM compute-in-memory macro for edge-AI. The design targets signed arithmetic, routing congestion, and switching overhead while supporting INT8 and BF16 computation.