D-Wave has demonstrated an error-detecting gate for scalable quantum architectures. The operation achieved approximately 99.9% fidelity while retaining dual-rail error detection.
NEO has combined two memory concepts for future AI processors. X-SRAM targets denser on-chip storage while 3D X-DRAM addresses external memory capacity.
Researchers moved one spin qubit across four isolated silicon registers. The five-qubit processor completed weight-four parity checks required by surface-code error correction.
CEA-Leti is moving three dimensional integration into future AI architectures. Fine pitch hybrid bonding is being developed alongside new approaches to power, memory, cooling, and test.