IN Brief:
- PicoJool has raised $27.5 million in Series A funding, taking disclosed funding to $39.5 million.
- Its portfolio includes 100G and 200G VCSELs plus lower-power microVCSEL arrays for AI optical interconnects.
- Funding will expand engineering and manufacturing operations in the US and Taiwan as products progress through qualification.
PicoJool has raised $27.5 million in Series A funding to expand development and manufacturing capacity for 200G VCSELs, microVCSEL arrays, and optical connectivity products aimed at high bandwidth AI data centre links.
The financing was led by Socratic Partners with participation from Hudson River Trading. It follows a $12 million seed round led by Playground Global and takes PicoJool’s disclosed funding to $39.5 million.
The company plans to expand research, operations, sales, and manufacturing teams in the US and Taiwan as it moves its optical semiconductor portfolio through customer qualification and towards broader availability. Early samples of its chip-level VCSEL products are already being supplied.
The current portfolio includes 100G and 200G vertical-cavity surface-emitting lasers alongside lower-power microVCSEL configurations operating at 50G NRZ and 64G NRZ or PAM4. PicoJool is targeting aggregate optical links from 800G through 1.6T and 3.2T as AI systems increase the volume of data moving between accelerators, switches, and memory resources.
VCSELs are well established in shorter-reach optical interconnects because they can be fabricated in arrays, coupled efficiently into multimode fibre, and manufactured using processes suited to high volume production. Extending those advantages to higher lane rates requires control over modulation bandwidth, optical power, thermal behaviour, reliability, and packaging.
PicoJool’s 200G devices exceed 37GHz bandwidth, while its microVCSEL platform takes a different approach by combining many lower-power lanes in parallel. The two strategies give system designers a choice between pushing more bandwidth through each optical channel and increasing the number of channels while reducing the energy required per bit.
The funding is therefore principally an industrialisation step. Demonstrating a high speed device is only the beginning of a semiconductor programme; wafers and packaged products then have to deliver predictable threshold current, optical output, wavelength, modulation response, reliability, and thermal behaviour across manufacturing lots.
PicoJool is working with WIN Semiconductor and other gallium arsenide foundries as it prepares the 200G devices for qualification and production. Foundry scale can provide manufacturing capacity, but it also places tighter demands on process windows, wafer-level test, yield monitoring, and design rules if devices developed in smaller runs are to behave consistently at volume.
The company’s roadmap extends beyond laser die. PicoJool plans active optical cable and near-packaged optics products and is working with system companies and hyperscale operators on pluggable, NPO, and co-packaged optical architectures.
Each format moves the boundary between electronics and optics. Conventional pluggable modules keep the optical transceiver accessible at the front of a system, while near-packaged and co-packaged designs move optical conversion progressively closer to switch or compute silicon. Shortening the electrical path can reduce signal loss and I/O power, but increases the thermal, mechanical, assembly, and service challenges surrounding the optical engine.
Those trade-offs make laser efficiency only one part of the overall power budget. Driver electronics, receiver circuitry, coupling loss, thermal control, packaging, and the electrical interface between processor and optical engine all contribute to the energy required to move each bit of data.
The Series A gives PicoJool additional resources to address those manufacturing and integration questions, but customer qualification remains the important next step. No named hyperscale deployment or general volume-production date has been announced, and early sampling still leaves reliability, yield, and module-level performance to be demonstrated at scale.
AI infrastructure is turning optical connectivity into a semiconductor manufacturing problem as much as a networking problem. Higher aggregate bandwidth has to arrive without allowing interconnect power and packaging complexity to consume an increasing share of the system budget. PicoJool’s next test is whether its high speed and massively parallel VCSEL approaches can maintain their performance advantages once they move from early devices into qualified, repeatable production.
