IN Brief:
- SiPearl and Egis have agreed processor technology cooperation and a related investment arrangement.
- Mobius100 is specified as a dual-die, 140-core architecture using Arm Neoverse V3 and UCIe 2.0.
- Engineering samples are targeted for 2027, with volume production proposed for the second half of 2028.
SiPearl and Taiwan’s Egis Group have signed technology cooperation and investment agreements to develop Mobius100, a modular server processor architecture intended to underpin SiPearl’s second-generation Rhea2 programme.
The platform is being developed with Alcor Micro, an Egis subsidiary, using Arm Neoverse V3 technology and a chiplet interconnect supplied through the Egis group. Engineering samples are targeted for 2027 and volume production for the second half of 2028, although those remain development objectives rather than completed manufacturing milestones.
Mobius100 is intended for high-performance computing, AI infrastructure and data centre applications. Its disclosed architecture comprises two semiconductor dies with 140 processor cores in total, including 12 redundant cores, and is designed for implementation using TSMC’s N3P manufacturing process.
The distinction between the physical core count and cores available for application work must be preserved. Redundant cores provide a mechanism for addressing selected manufacturing or reliability constraints, but their presence does not establish the delivered performance of a qualified processor.
Chiplet architectures divide parts of a system across multiple dies rather than implementing every function in one monolithic semiconductor. This can give designers more flexibility in how processors, interfaces and accelerators are developed and assembled, but it transfers some integration complexity into the package and its die-to-die connections.
Those connections must maintain signal integrity and timing while delivering the bandwidth required by the cooperating dies. Power distribution, clocking, heat removal and differences in thermal expansion also affect whether a package can operate reliably at the intended frequency and power levels.
Mobius100 will use Universal Chiplet Interconnect Express technology. Egis subsidiary InPsytech is contributing UCIe 2.0 intellectual property, with the proposed processor specified to provide eight UCIe 2.0-S interfaces for integration with compatible chiplets and acceleration functions.
UCIe defines an approach to communication between dies inside a package, giving suppliers a common basis for electrical and protocol design. Compatibility with the standard does not automatically resolve interoperability: engineers must verify link training, clock domains, error handling, power states and any coherency mechanisms required when separately developed components operate together.
The Mobius100 specification also includes DDR5-12800 MRDIMM memory connectivity, PCIe Gen6 and Compute Express Link interfaces. These technologies are intended to support memory-intensive workloads and connections to external accelerators or compatible resources, subject to the implementation and qualification of the final silicon.
High-performance processors can be constrained by the rate at which information moves between processing cores, memory and attached devices. Wider or faster interfaces offer potential improvements, but effective throughput depends on access patterns, memory configuration, software and the overhead introduced by communication between components.
Arm Scalable Vector Extension 2 is included in the proposed design for compatible vector workloads. Applications and compilers must use the relevant instructions before that capability can contribute to performance, and no published benchmarks yet demonstrate how the processor behaves in representative computing systems.
The planned security features include a Caliptra 2.0-based hardware root of trust and Arm Confidential Compute Architecture with Realm Management Extension capabilities. They are intended to support protected execution and the authentication of platform software, but their effectiveness will depend on firmware, system integration and operational configuration.
SiPearl’s Rhea2 work follows its first-generation Rhea1 processor, for which the company delivered initial samples to Bull for integration with the BullSequana XH3000 platform associated with Germany’s JUPITER supercomputer. That delivery is separate from the OpenCUBE consortium’s milestone involving a Seine server delivered to HPE; the latter should not be represented as a further Rhea1 sample shipment.
Egis is also developing a wider chiplet ecosystem through which processor and specialised functions could be combined in more tailored computing packages. Making that approach commercially useful requires access to tested components, reliable assembly processes and software support as well as agreed electrical interfaces.
Assembly yield will be a particular consideration for a multi-die design. Individual dies must be tested before integration, and the completed package must then meet requirements for interconnect integrity, thermal behaviour and long-term reliability. Problems in any of those stages can affect the economics of production even if the underlying chiplets perform correctly.
The agreements include Egis participation in SiPearl’s financing arrangements, although the public disclosures do not establish a completed investment value or detailed transaction terms. The collaboration is therefore best described through the technical programme and the announced investment relationship rather than an assumed cash amount or equity stake.
Mobius100 has not yet reached qualified production silicon. Tape-out, physical assembly, system validation and performance testing remain ahead of the projected 2027 engineering samples, while the proposed 2028 production ramp will depend on those results and customer requirements. Rhea2 will build on that work rather than constituting an already delivered processor.
