IN Brief:
- The 3U VPX336A combines GNSS, PTP, SyncE, IRIG-B, 1PPS, and conventional clock interfaces.
- Five DPLLs provide jitter cleaning and automatic holdover, with an OCXO supporting up to 24 hours after reference loss.
- VITA 46.11 Tier 3 management and an optional six-axis IMU support integration into rugged sensor platforms.
VadaTech has introduced the VPX336A, a rugged 3U VPX timing module combining GNSS, IEEE 1588 Precision Time Protocol, Synchronous Ethernet, IRIG-B, and 1PPS interfaces for defence and aerospace systems that require a common time and frequency reference.
The board integrates five digital phase locked loops with an oscillator architecture designed for jitter cleaning, reference selection, and holdover. VadaTech says the module can accept timing or frequency from several upstream sources and distribute synchronised outputs through network, serial, clock, and VPX interfaces.
Input options include GNSS for frequency, time, location, velocity, and associated metadata; IEEE 1588 PTP for frequency and time; IRIG-B; 1PPS; a sine wave clock input; and Synchronous Ethernet. Outputs can include PTP, IRIG-B, 1PPS, NMEA, conventional clock signals, and SyncE depending on system configuration.
The digital phase locked loop operates from 1Hz to 750MHz and is used to clean noisy references before distributing them through the system. VadaTech specifies acquisition of a 1Hz reference in between three and 60 seconds depending on the source. If the selected external reference disappears, the module automatically enters holdover and continues supplying timing and frequency outputs.
Holdover is supported by an oven controlled crystal oscillator and algorithms that learn oscillator ageing and thermal behaviour during locked operation. VadaTech specifies support for up to 24 hours without an atomic clock where that holdover period is sufficient for the system requirement.
That capability is particularly relevant to platforms where the temporary loss of GNSS or network timing cannot be allowed to break synchronisation between sensors, radios, processors, or data acquisition hardware. Radar, electronic warfare, communications, and distributed measurement systems may all depend on deterministic timing relationships after their preferred external reference becomes unavailable.
The VPX336A can operate in grandmaster and slave clock modes and is aligned with an Open Group Sensor Open Systems Architecture profile. It also implements VITA 46.11 Tier 3 hardware management, allowing status and health information from the timing card to be incorporated into the platform management structure of a VPX chassis.
An optional inertial measurement unit adds a triaxial digital gyroscope and triaxial accelerometer, with data accessible over Ethernet or PCIe. The card also provides front panel 1000BASE-T or Gigabit Ethernet through an LC optical module, with network ports supporting IEEE 1588 PTP and SyncE.
The combination allows the board to bridge timing methods that frequently coexist in complex embedded systems. PTP distributes time over Ethernet, SyncE provides network frequency, IRIG-B remains established in aerospace and test systems, and GNSS provides an external absolute reference. Integrators otherwise need separate hardware or additional translation stages when those timing domains have to be connected.
Placing the functions on a 3U VPX board keeps timing inside the same modular architecture as compute, FPGA, data conversion, and network hardware. That can reduce external cabling and simplify integration, although the timing subsystem then shares the chassis thermal, electrical, and backplane environment with other high performance electronics.
The oscillator, jitter cleaning, and holdover functions are intended to preserve timing quality through those conditions and through temporary loss of an external reference. The optional IMU also gives systems a local source of motion information where timing and navigation functions are being combined on one platform.
The module addresses a broader move towards open, modular sensor architectures in defence electronics. Standard VPX hardware allows timing, processing, networking, and data conversion cards from different suppliers to share a common chassis, but system-level synchronisation remains one of the functions that has to work across every module rather than inside a single board.
VadaTech has not published pricing or a general availability date in the announcement. Its current VPX336A product page also remains without a product photograph, so the technical specification is ahead of the marketing material normally associated with a completed hardware launch.
The 24-hour holdover figure provides a useful boundary for system design. Applications requiring longer autonomous timing, tighter holdover accuracy, or operation through extended denial of external references may still need an atomic source or a separate resilient timing architecture. Within that boundary, the VPX336A consolidates several timing standards and management functions onto one rugged embedded card.
