IN Brief:
- Qualitas is supplying integrated high-speed interface IP for Mobilint's NPU-based AI system-on-chip development.
- The design includes heterogeneous UCIe chiplet connectivity, a PCIe subsystem, and MIPI interfaces for camera and display data.
- The project targets an advanced semiconductor process and eventual mass production, although no production date or final device specification has been disclosed.
Qualitas Semiconductor is supplying integrated high-speed interface intellectual property for an AI system-on-chip being developed by South Korean semiconductor company Mobilint. The collaboration combines chiplet interconnect technology, PCIe communication, and MIPI camera and display interfaces within an advanced processor design incorporating a neural processing unit.
Qualitas is providing several interface subsystems rather than an individual standalone IP block. The arrangement covers communication between semiconductor dies, high-speed connections to external devices, and the transfer of imaging and display data, with the companies targeting an eventual production design.
Mobilint develops neural-network processing hardware for embedded AI applications, including robotics and machine perception. The companies have not disclosed the final processor specifications, manufacturing process node, initial production date, or the volumes expected from the project.
An NPU-based system-on-chip must move information between memory resources, computing engines, and peripheral interfaces. The amount of processing performed by the neural accelerator is important, but the rate at which data can enter and leave the device also affects application performance.
In a robotic vision system, image data may be received from several cameras, stored or buffered in memory, processed by neural-network hardware, and combined with other information before a control decision is made. Delays in moving the data can affect the time available for the processing and control functions.
The MIPI subsystem supplied by Qualitas addresses part of the camera and display interface requirement. MIPI CSI is widely used for connections carrying image information into processing hardware, while MIPI DSI supports communication between processors and displays.
Integrating these interfaces can reduce the need for separate external interface components, but their operation must still be coordinated with the processor’s internal memory and data paths. Camera resolution, frame rate, pixel format, and buffering requirements all contribute to the bandwidth required by an imaging application.
The PCIe subsystem provides another route for transferring information. PCIe is used for high-speed connections to equipment including storage controllers, networking hardware, accelerators, and other processing devices.
Its performance depends on the implemented interface generation, lane configuration, controller capabilities, and the attached equipment. A processor supporting high-speed PCIe communication still requires an internal architecture capable of moving data to and from the connected devices at an appropriate rate.
Qualitas is also supplying chiplet connectivity designed around heterogeneous Universal Chiplet Interconnect Express, or UCIe, communication. The arrangement is intended to support connections between semiconductor dies that may use different internal architectures.
Chiplet-based designs divide selected functions between multiple dies within a larger semiconductor package. The approach can provide flexibility when reusing processing blocks or combining functions manufactured using different semiconductor technologies.
Dividing a design between dies introduces additional electrical and mechanical requirements. Information that would otherwise move across an internal on-die connection must pass through an inter-die interface and the surrounding package structure.
The transmission channel must maintain signal integrity at the required data rate while operating within power and physical-area constraints. Package connections, conductor geometry, interference, and the electrical characteristics of the transmitter and receiver all influence the result.
Qualitas identifies equalisation and clock-and-data recovery as important technologies within its high-speed interface development. Equalisation compensates for distortion introduced during signal transmission, while clock-and-data recovery reconstructs the timing needed to interpret incoming serial data.
As serial data rates rise, the available timing and voltage margins can become smaller. Interface design must account for channel loss, noise, jitter, and variations in semiconductor manufacturing and operating conditions.
Advanced process nodes introduce further integration challenges. Digital logic and high-speed analogue interface circuitry do not necessarily respond to transistor scaling in the same way, requiring physical design, verification, and power management to accommodate different circuit characteristics.
Qualitas says its integrated offering includes physical-layer and controller IP. Combining those elements into defined subsystems can reduce the amount of integration work required by the SoC developer, although the completed design must still be verified with its processing, memory, and peripheral architecture.
Comprehensive verification is particularly important when several interfaces operate concurrently. Activity on one connection can influence power consumption and electrical noise, while shared processing and memory resources may introduce contention between data streams.
The developer must therefore assess the interfaces both individually and as part of the complete processor. Functional verification, timing analysis, physical design, and system-level performance testing all contribute to establishing whether the device meets its intended requirements.
Qualitas has existing expertise in PCIe, UCIe, and MIPI technology, including interface implementations developed for advanced semiconductor processes. The Mobilint project extends that work into an integrated combination of several subsystems within one NPU-based design.
The collaboration follows previous interface and video-processing IP activity involving Mobilint, including its adoption of Chips&Media codec technology for AI semiconductor products. The Qualitas development concerns a separate set of functions associated with inter-die communication and external connectivity.
No benchmark results or final interface operating speeds have been released for the new Mobilint processor. The disclosed development is the integration of several high-speed interface subsystems into a chip design intended for eventual mass production, with further verification and manufacturing milestones still to be established.
