Category: Memory
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SK hynix has mapped optical interconnect scaling beyond current HBM. The roadmap targets bandwidth, energy, and latency bottlenecks across next-generation AI compute and memory systems.
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Prodigy has launched a UFS 5.0 protocol validation platform commercially. PGY-UFS5-EX-PA supports 46.64Gbps per lane, PAM4 acquisition, continuous capture, decoding, packet triggering, and error analysis.
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Micron has launched a decade-long programme for advanced semiconductor research. The planned $10bn investment spans future memory, compute architectures, advanced packaging, and manufacturing technology.
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Sandisk is reshaping NAND development around AI storage requirements now. Its roadmap combines bonded CMOS, denser QLC flash, HBF, and longer-term customer capacity agreements.
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Enterprise SSDs now consume nearly half of global NAND shipments. Counterpoint says AI inference lifted their share to 48% of NAND bits in Q2, while YMTC entered the shipment top three.
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Altera has expanded Agilex memory support through Quartus 26.1.1 software. The update adds DDR5-6400 and LPDDR5-6400 on Agilex 7 M-Series devices, alongside broader low-power memory options elsewhere in the portfolio.
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Researchers have demonstrated a 28nm SRAM compute-in-memory macro for edge-AI. The design targets signed arithmetic, routing congestion, and switching overhead while supporting INT8 and BF16 computation.
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TrendForce expects DRAM constraints to reshape future HBM configurations significantly. Accelerator developers are evaluating lower-capacity options as supply and validation pressures persist.
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Samsung has presented vertical memory concepts for future AI systems. zHBM places memory above accelerators, while zNAND-O targets dense, low-latency edge storage.
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Infineon’s 512Mb NOR Flash has qualified for MediaTek’s C-X1 platform. The approval gives automotive developers a validated boot memory option for software-defined cockpit systems.